onsemi NP3100SCT3G
- Part No.:
- NP3100SCT3G
- Manufacturer:
- onsemi
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
NP3100SCT3G.pdf
- Description:
- THYRISTOR 275V 100A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:2,890
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
NP3100SCT3G from onsemi is a bidirectional thyristor surge protector (TSPD) designed for overvoltage clamping in telecom line interfaces. It features 275 V peak off-state voltage (VDRM), 350 V breakover voltage (VBO), 4.0 V on-state voltage (VT), 150 mA holding current (IH), and supports 500 A(pk) 10×1000 µs surge current per GR-1089-CORE. It protects central office, access, and customer premises equipment.
For engineers reviewing the NP3100SCT3G datasheet, pinout, applications, or equivalent options, this page delivers verified electrical parameters, SMB package dimensions, telecom regulatory compliance (GR-1089-CORE, ITU-T K.20/21/45, TIA-968-A), thermal resistance (90 °C/W), and validated alternative parts for telecom surge protection design.
Technical Context
The NP3100SCT3G operates as a voltage-triggered crowbar device: it remains high-impedance below VDRM (275 V), switches to low-impedance conduction at VBO (350 V), and latches until current falls below IH (150 mA). Its bidirectional symmetry enables single-device protection of AC-coupled telecom lines without polarity concerns.
It meets GR-1089-CORE Level C surge immunity (50 A(pk), 10×1000 µs) and ITU-T K.20/21 (75 A(pk), 10×700 µs), with 5.0 kV/µs critical dv/dt rating and 500 A/µs di/dt capability. Capacitance is 31 pF at 1 MHz, minimizing signal distortion in voice/data lines.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDRM | 275 V - Maximum continuous off-state voltage before triggering; sets operating margin for 24–48 V telecom systems. |
| VBO | 350 V - Breakover voltage threshold where device switches to low-impedance state to divert surge energy. |
| IH | 150 mA - Minimum current required to maintain conduction after triggering; ensures reliable latch-off during low-current surges. |
| VT | 4.0 V - On-state voltage drop at 1.0 A(pk); determines power dissipation (4 W peak) during clamping. |
| CO | 31 pF - Junction capacitance at 1 MHz/2 Vdc; preserves signal integrity in broadband voice and DSL applications. |
| dv/dt | 5.0 kV/µs - Minimum rate of voltage rise that avoids false triggering; critical for noisy telecom environments. |
| TJ Range | −40 to +150 °C - Full industrial temperature operation; supports deployment in uncontrolled central office cabinets. |
Pinout & Package
NP3100SCT3G uses the SMB (DO-214AA, Case 403C) surface-mount package: 4.06–4.57 mm length, 3.30–3.81 mm width, 1.90–2.41 mm height, with gull-wing leads. Thermal resistance is 90 °C/W (Junction-to-Ambient, FR4 3″×4.5″ board).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MT1 | Main Terminal 1 | Anode/cathode terminal for bidirectional conduction; symmetric with MT2-no polarity assignment required. |
| MT2 | Main Terminal 2 | Second main terminal; interchangeable with MT1 in bidirectional operation; forms clamping path across protected line pair. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional clamping | Enables single-device protection of AC-coupled telecom lines (e.g., POTS, xDSL) without external diodes or polarity selection. |
| GR-1089-CORE Level C compliance | Validated for 50 A(pk) 10×1000 µs surge immunity-meets stringent central office equipment requirements. |
| Low 31 pF capacitance | Minimizes insertion loss and phase distortion in voice-band (300–3400 Hz) and ADSL2+ (up to 2.2 MHz) signals. |
| Pb-free, RoHS-compliant SMB package | Supports lead-free reflow assembly (JEDEC J-STD-020) and environmental compliance for global telecom deployments. |
| 150 °C max junction temperature | Enables reliable operation in high-ambient telecom cabinets without derating under sustained surge duty cycles. |
Applications
| Central Office Line Card Protection | xDSL Customer Premises Equipment |
|---|---|
|
Use Scenario: Protecting analog line interface circuits (SLIC, codec, hybrid) on carrier-grade line cards exposed to lightning-induced surges on outside plant wiring. IC Role / Device Role / Timing Role: Crowbar-type overvoltage protector placed across tip/ring terminals to clamp transients before they reach sensitive SLIC ICs. Use Value: Prevents damage to $5+ SLIC ICs by diverting up to 500 A(pk) (2×10 µs) while maintaining <4 V clamping voltage during conduction. |
Use Scenario: Surge suppression on telephone line inputs of residential DSL modems and gateways subjected to induced surges from nearby power lines. IC Role / Device Role / Timing Role: Bidirectional transient voltage suppressor connected between line pair and ground, triggered only during overvoltage events. Use Value: Enables compliance with ITU-T K.21 (10×700 µs, 75 A(pk)) without adding series impedance or degrading ADSL signal-to-noise ratio (SNR). |
| VoIP Gateway Analog FXS Port | Industrial PBX Interface Module |
|
Use Scenario: Safeguarding FXS (Foreign Exchange Station) ports in enterprise VoIP gateways against accidental AC power cross-connects and ESD events. IC Role / Device Role / Timing Role: Primary overvoltage protector located at line entry point, upstream of transformer and common-mode choke. Use Value: Latches at 150 mA holding current to sustain clamping during prolonged overvoltages (e.g., 48 V DC fault), preventing thermal runaway in downstream components. |
Use Scenario: Protecting analog station ports in ruggedized industrial PBX systems deployed in factory environments with high EMI and ground potential differences. IC Role / Device Role / Timing Role: High-reliability surge protector rated for −40 to +150 °C operation, mounted directly on PCB near connector. Use Value: Delivers 90 °C/W thermal resistance on standard FR4, enabling stable performance without heatsinking in space-constrained chassis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge protector applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NP3100SAT3G | Same VDRM/VBO/IH specs, but rated for GR-1089-CORE Level A (150 A(pk), 2×10 µs) instead of Level C. | Targeted at less severe surge environments (e.g., interior building wiring), not outdoor plant exposure. | Select NP3100SAT3G when system-level testing confirms Level A immunity suffices and higher surge margin is unnecessary. |
| NP3100SBT3G | Identical electrical specs and GR-1089-CORE Level B (90 A(pk), 10×160 µs) rating; differs only in marking code (310B vs. 310C). | Suitable for intermediate surge threat profiles such as multi-dwelling unit (MDU) distribution points. | Choose NP3100SBT3G when Level B compliance is validated for the installation environment and inventory simplification is prioritized. |
Compared with NP3100SAT3G and NP3100SBT3G, the NP3100SCT3G provides the highest validated surge immunity (Level C) within the same SMB footprint and electrical family-making it the default choice for central office and outside plant–facing telecom equipment requiring maximum robustness.
Availability
NP3100SCT3G is available at Aetrix Electronics and suitable for central office line cards, xDSL customer premises equipment, VoIP gateway FXS ports, industrial PBX interface modules, and telecom network interface units requiring stable component supply and long-term lifecycle support.
Supply support for NP3100SCT3G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier specializing in energy-efficient power, analog, sensor, and logic solutions for automotive, industrial, cloud, and telecom markets.
The NP Series thyristor surge protectors were engineered specifically for telecom infrastructure protection-delivering bidirectional, high-surge-capacity clamping in compact SMB packages compliant with GR-1089-CORE, ITU-T K.20/21/45, and TIA-968-A standards.
FAQ
What is the peak off-state voltage rating of the NP3100SCT3G?
The NP3100SCT3G has a peak off-state voltage (VDRM) rating of 275 V. This specifies the maximum repetitive voltage the device can block in its off state without triggering. It is measured across MT1 and MT2 terminals under specified test conditions (TA = 25°C), and defines the safe operating margin for telecom line voltages up to 48 V nominal with transient headroom. The NP3100SCT3G maintains this rating across its full −40 to +150 °C operating temperature range.
How does the NP3100SCT3G differ from other variants like NP3100SAT3G and NP3100SBT3G?
The NP3100SCT3G shares identical electrical specifications (VDRM, VBO, IH, VT) with NP3100SAT3G and NP3100SBT3G but is qualified to GR-1089-CORE Level C (50 A(pk), 10×1000 µs), whereas NP3100SAT3G is Level A (150 A(pk), 2×10 µs) and NP3100SBT3G is Level B (90 A(pk), 10×160 µs). All three use the same SMB package and marking format (310A/310B/310C), making them mechanically interchangeable. The NP3100SCT3G is selected when Level C compliance is mandatory.
What is the thermal resistance of the NP3100SCT3G, and how does it impact layout design?
The NP3100SCT3G has a junction-to-ambient thermal resistance (RθJA) of 90 °C/W, measured per EIA/JESD51-3 on a 3″×4.5″ FR4 board with 2 oz copper. This value guides PCB copper area allocation: for sustained 1 A(pk) clamping events, ~4 W dissipation requires careful thermal relief. Layout should avoid enclosing the SMB body in large copper pours without thermal vias, and ensure ≥2 mm clearance from heat-sensitive components. The NP3100SCT3G's 150 °C max junction temperature allows operation without active cooling in most telecom enclosures.
Does the NP3100SCT3G require external triggering circuitry?
No, the NP3100SCT3G is a self-triggering, voltage-activated thyristor surge protector. It requires no external gate drive, bias, or control signals. Conduction initiates automatically when voltage across MT1–MT2 exceeds VBO (350 V), and the device remains latched until current falls below IH (150 mA). This intrinsic behavior eliminates complexity in telecom line card designs and ensures deterministic response to fast-rising surges per ITU-T K.20/21 test waveforms.
Is the NP3100SCT3G compliant with RoHS and lead-free assembly requirements?
Yes, the NP3100SCT3G is Pb-free and RoHS-compliant, as indicated by the "G" suffix in its part number. It meets JEDEC J-STD-020 moisture sensitivity level (MSL) 1 and is qualified for standard lead-free reflow profiles (peak temperature ≤260 °C). The SMB package uses matte tin-plated leads compatible with no-clean and water-wash flux chemistries. This ensures seamless integration into modern telecom manufacturing lines without process modification.
NP3100SCT3G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Package/Case:
- DO-214AA, SMB
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 350V
- Voltage - Off State:
- 275V
- Voltage - On State:
- 4 V
- Current - Peak Pulse (8/20µs):
- -
- Current - Peak Pulse (10/1000µs):
- 100 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 76pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
NP3100SCT3G FAQ
1.How can I place an order for NP3100SCT3G through Aetrix?
Please submit a Request for Quotation (RFQ) for NP3100SCT3G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for NP3100SCT3G reliable?
The price and inventory of NP3100SCT3G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for NP3100SCT3G is usually 5 days.
3.What payment methods are accepted for NP3100SCT3G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for NP3100SCT3G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for NP3100SCT3G?
NP3100SCT3G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your NP3100SCT3G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for NP3100SCT3G?
For technical support, including NP3100SCT3G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your NP3100SCT3G requirements.
6.How does Aetrix verify that NP3100SCT3G is sourced from the original manufacturer or authorized distributors?
All NP3100SCT3G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that NP3100SCT3G meets industry standards.
7.What is the process for return or replacement of NP3100SCT3G?
All NP3100SCT3G units undergo pre-shipment inspection (PSI). If there is an issue with NP3100SCT3G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The NP3100SCT3G part is unused and in its original packaging.
Return procedure for NP3100SCT3G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
NP3100SCT3G Tags

-
TISP4015L1AJR-S
Bourns Inc.

-
TISP4015L1BJR-S
Bourns Inc.

-
SMP100LC-270
STMicroelectronics

-
TISP4240M3BJR-S
Bourns Inc.

-
SMP100LC-35
STMicroelectronics

-
SMP100LC-65
STMicroelectronics

-
SMP100LC-8
STMicroelectronics

-
TISP4P035L1NR-S
Bourns Inc.

-
TISP4350H3BJR-S
Bourns Inc.

-
TISP4011H1BJR-S
Bourns Inc.

-
SMP100LC-400
STMicroelectronics

-
P0300SALRP
Littelfuse Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

