Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Renesas P8620-I0NLGI

Name: P8620-I0NLGI
Brand: Renesas
SKU: P8620-I0NLGI
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: P8620-I0NLGI

Manufacturer:: Renesas

Category:: Power Management - Specialized

Package:: -

Datasheet:: P8620-I0NLGI.pdf

Description:: P8620-I0 NEXT GENERATION SOC PMI

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,075

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

P8620-I0NLGI from Renesas Electronics is a Cortex™ M0-based programmable multi-channel Power Management IC (PMIC) designed for Intel Tiger Lake UP3/Cornestone Ridge and Tiger Lake H/Whale Mountain reference platforms. It integrates four internal buck regulators (1.3A each), five DPU controllers, three LDOs, two 10-bit ADCs, SPI/I²C/SVID interfaces, and 16 GPIOs - delivering full VR 13.0 compliance and rail-level sequencing, current monitoring, and fault reporting in a single 9×9 mm 64-QFN package.

For engineers reviewing the P8620-I0NLGI datasheet, P8620-I0NLGI pinout, P8620-I0NLGI application, or P8620-I0NLGI equivalent, key selection considerations include Intel VR 13.0 compliance, distributed power architecture with up to 29A pulsed load support per rail, firmware-defined functionality, integrated current/voltage/temperature sensing, and thermal performance in industrial ambient conditions (-40°C to +85°C).

Technical Context

The P8620-I0NLGI implements a hierarchical PMIC architecture: a host MCU (ARM Cortex-M0) manages four integrated buck regulators and five external DPU controllers via a proprietary single-wire digital bus. Each rail supports independent voltage configuration (0.3V–1.5V), sequencing control, and real-time IMON-based current measurement using dedicated sense paths (GSNS0–GSNS4).

It delivers Intel VR 13.0-compliant SVID communication (SVID_CLK/SVID_DATA/SVID_ALRT/SVID_SYNC_B), high-speed SPI (up to 8 MHz) and I²C (up to 3.4 Mbps), and safety-critical diagnostics including overvoltage/overcurrent/fault reporting via FAULT pin and MCU_NOTIFY_B interrupt signaling.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	4.2V to 5.5V - powers all internal regulators and logic from a single mid-rail supply.
Buck Regulators	Four 1.3A internal FET buck converters - one configurable as ±0.65A source/sink for dynamic rail reversal.
DPU Controllers	Five independent buck controllers - each drives external P8610 DPUs; supports up to 29A pulsed load per rail.
ADC Resolution	Two 10-bit ADCs - monitor up to 7 external voltages, die temperature, and 5 rail currents via GSNS inputs.
Communication Interfaces	SPI (8 MHz), I²C (3.4 Mbps), SVID - enables host SOC coordination of power states, margins, and telemetry.
GPIO Count	16 programmable GPIOs - including GPP15HV (high-voltage capable) for external OVP switch control.
Operating Temperature	-40°C to +85°C ambient - qualified for industrial embedded systems requiring extended thermal stability.
Package	64-QFN, 9 × 9 mm, 0.5 mm pitch, 7.7 × 7.7 mm exposed pad - optimized for thermal dissipation in dense SoC power delivery.

Pinout & Package

The P8620-I0NLGI is housed in a thermally enhanced 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with a 7.7 × 7.7 mm exposed thermal pad (EPAD). Pin functions are firmware-defined but fixed per hardware revision; pin mapping is validated per R16DO0026EU0101 Rev.1.01.

Pin/Terminal	Circuit Role	Design Meaning
GPP0/PMIC_EN	Enable Input	Active-high global enable; asserts internal bias and initiates power-up sequence.
SVID_CLK / SVID_DATA / SVID_ALRT / SVID_SYNC_B	SVID Interface	Intel VR 13.0-compliant serial interface for voltage setpoint, margining, and fault reporting to host SOC.
SPI_MISO / SPI_MOSI / SPI_CLK / SPI_CS_B	SPI Interface	Full-duplex master/slave interface supporting configuration, telemetry readback, and firmware updates at ≤8 MHz.
I2C_SDA / I2C_SCL	I²C Interface	Standard/fast-mode-plus (3.4 Mbps) slave interface for secondary host access or system management controller.
GSNS0–GSNS4	Current Sense Inputs	Dedicated analog inputs for measuring DC/DC rail currents via external shunts; routed to internal 10-bit ADCs.
DCD0_LX–DCD3_LX	Buck Switch Nodes	Power switch outputs for four internal buck regulators; require external inductors and output capacitors.
CTRL0_FB–CTRL4_FB	DPU Feedback Inputs	Analog feedback inputs for five external DPU controllers; enable closed-loop regulation of remote rails.
FAULT / MCU_NOTIFY_B	Interrupt Outputs	Open-drain status alerts: FAULT signals critical faults; MCU_NOTIFY_B signals firmware-triggered events to host.

Key Features

Feature	Design Value
Firmware-Defined Functionality	ARM Cortex-M0 core with 4 kB RAM + ECC and 4 kB ROM executes platform-specific firmware - enabling field-upgradable behavior without hardware change.
Distributed Power Architecture	Five DPU controllers coordinate with up to four P8610 DPUs per rail, scaling total pulsed current to 29A while maintaining tight transient response and thermal distribution.
Rail-Level Diagnostics	Real-time monitoring of voltage, current (via GSNS), and temperature across all rails - supports failure analysis, usage logging, and debug trace without external instrumentation.
Multi-Protocol Digital Control	Simultaneous SVID (for Intel SOC), SPI (for firmware/config), and I²C (for BMC/system manager) interfaces - eliminates need for protocol translation bridges.
Configurable Source/Sink Buck	One 1.3A buck regulator supports ±0.65A bidirectional operation - enables active discharge, dynamic voltage positioning, and rail reversal in memory or I/O subsystems.
Industrial Thermal Rating	Rated for -40°C to +85°C ambient operation with thermally enhanced 64-QFN package - ensures reliability in uncontrolled industrial environments.

Applications

Intel Tiger Lake UP3 CRB Power Delivery	Intel Tiger Lake H CRB Power Delivery
Use Scenario: Power management for Intel Tiger Lake UP3 SoC on customer reference board with dual-core CPU, integrated GPU, and LPDDR4x memory. IC Role / Device Role / Timing Role: Primary PMIC providing VCCIN, GT, SOC, and memory rails with VR 13.0-compliant SVID handshake and dynamic voltage/frequency scaling. Use Value: Enables full compliance with Intel's power delivery specification while reducing BOM count by integrating sequencing, monitoring, and protection in one device.	Use Scenario: Power solution for Intel Tiger Lake H-series SoC on Whale Mountain CRB targeting high-performance mobile workstations. IC Role / Device Role / Timing Role: Host PMIC managing CPU core, graphics, SoC, and I/O power domains with coordinated rail sequencing and current telemetry. Use Value: Delivers precise rail timing control and real-time current feedback to support aggressive turbo boost and thermal throttling algorithms.
Industrial Edge AI Compute Module	Embedded Vision System with FPGA Co-Processor
Use Scenario: Compact industrial compute module requiring robust, programmable power for Intel SoC and peripheral interfaces in fanless enclosures. IC Role / Device Role / Timing Role: Centralized power controller handling multiple voltage domains, thermal monitoring, and fault-safe shutdown under wide ambient temperature swings. Use Value: Eliminates discrete sequencing ICs and external ADCs, reducing PCB area and improving long-term supply continuity for industrial OEMs.	Use Scenario: Vision system combining Intel SoC and Xilinx Artix-7 FPGA, demanding tightly coupled power sequencing and rail current visibility. IC Role / Device Role / Timing Role: Dual-role PMIC supplying SoC rails and generating FPGA auxiliary voltages while synchronizing startup/shutdown sequences across both devices. Use Value: Uses programmable GPIOs and SVID to coordinate power states between heterogeneous processors, avoiding race conditions during boot and sleep transitions.

Intel Tiger Lake UP3 CRB Power Delivery

Intel Tiger Lake H CRB Power Delivery

Use Scenario: Power management for Intel Tiger Lake UP3 SoC on customer reference board with dual-core CPU, integrated GPU, and LPDDR4x memory.

IC Role / Device Role / Timing Role: Primary PMIC providing VCCIN, GT, SOC, and memory rails with VR 13.0-compliant SVID handshake and dynamic voltage/frequency scaling.

Use Value: Enables full compliance with Intel's power delivery specification while reducing BOM count by integrating sequencing, monitoring, and protection in one device.

Use Scenario: Power solution for Intel Tiger Lake H-series SoC on Whale Mountain CRB targeting high-performance mobile workstations.

IC Role / Device Role / Timing Role: Host PMIC managing CPU core, graphics, SoC, and I/O power domains with coordinated rail sequencing and current telemetry.

Use Value: Delivers precise rail timing control and real-time current feedback to support aggressive turbo boost and thermal throttling algorithms.

Industrial Edge AI Compute Module

Embedded Vision System with FPGA Co-Processor

Use Scenario: Compact industrial compute module requiring robust, programmable power for Intel SoC and peripheral interfaces in fanless enclosures.

IC Role / Device Role / Timing Role: Centralized power controller handling multiple voltage domains, thermal monitoring, and fault-safe shutdown under wide ambient temperature swings.

Use Value: Eliminates discrete sequencing ICs and external ADCs, reducing PCB area and improving long-term supply continuity for industrial OEMs.

Use Scenario: Vision system combining Intel SoC and Xilinx Artix-7 FPGA, demanding tightly coupled power sequencing and rail current visibility.

IC Role / Device Role / Timing Role: Dual-role PMIC supplying SoC rails and generating FPGA auxiliary voltages while synchronizing startup/shutdown sequences across both devices.

Use Value: Uses programmable GPIOs and SVID to coordinate power states between heterogeneous processors, avoiding race conditions during boot and sleep transitions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ISL95852IRZ-T	Single-chip 4-phase VR13-compatible controller with integrated drivers; no ARM MCU or DPU support; lacks ADC/GPIO flexibility.	Targeted at simpler Intel client platforms without distributed power or telemetry requirements.	Choose ISL95852IRZ-T only if firmware programmability, rail-level current sensing, and DPU expansion are unnecessary.
TPS65988DHAR	USB-C PD/Type-C port controller with integrated buck converters; not VR13.0 compliant; no SVID interface or DPU architecture.	Designed for USB-C power delivery and display port alternate mode - not suitable for Intel SoC core power.	TPS65988DHAR is incompatible for Intel VR13.0 applications; consider only for Type-C peripheral power management.

Compared with ISL95852IRZ-T and TPS65988DHAR, the P8620-I0NLGI uniquely combines VR13.0 SVID compliance, firmware-defined behavior, distributed DPU control, and comprehensive rail telemetry - making it the only option among the three that supports scalable, diagnostic-rich, Intel-certified SoC power delivery in industrial form factors.

Availability

P8620-I0NLGI is available at Aetrix Electronics and suitable for Intel Tiger Lake-based industrial edge computing, embedded vision systems, and ruggedized CRB deployments requiring stable component supply, long-lifecycle support, and verified thermal performance across -40°C to +85°C.

Supply support for P8620-I0NLGI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader headquartered in Tokyo, Japan, specializing in microcontrollers, analog power, and SoC solutions for automotive, industrial, and infrastructure markets.

The P8620-I0NLGI belongs to Renesas' programmable PMIC product line, engineered specifically to meet Intel VR13.0 specifications for high-performance industrial SoCs - emphasizing firmware adaptability, distributed power scalability, and real-time system diagnostics.

FAQ

What is the primary function of the P8620-I0NLGI in an Intel SoC platform?

The P8620-I0NLGI serves as the central power management IC for Intel Tiger Lake UP3 and Tiger Lake H SoCs, delivering VR13.0-compliant voltage regulation, rail sequencing, current/voltage/temperature telemetry, and fault reporting. Its ARM Cortex-M0 core executes platform-specific firmware to configure all five DPU controllers and four internal buck regulators - making the P8620-I0NLGI essential for certified power delivery in Intel reference designs.

Does the P8620-I0NLGI support Intel VR13.0 SVID communication?

Yes, the P8620-I0NLGI fully supports Intel VR13.0 SVID communication via dedicated pins (SVID_CLK, SVID_DATA, SVID_ALRT, SVID_SYNC_B), enabling dynamic voltage setting, margining, and fault reporting to the host Intel SoC. This SVID interface is hardware-implemented and validated per R16DO0026EU0101 Rev.1.01 - a core requirement for P8620-I0NLGI deployment in Tiger Lake CRBs.

How many external DPUs can the P8620-I0NLGI control, and what is the maximum pulsed load current per rail?

The P8620-I0NLGI incorporates five independent DPU controllers, each capable of driving up to four P8610 DPUs. This architecture supports up to 29A of pulsed load current per rail - verified in Renesas' reference implementation for Intel Tiger Lake platforms. The P8620-I0NLGI coordinates all DPUs via a proprietary single-wire digital bus, ensuring synchronized control and status exchange without additional host intervention.

What interfaces does the P8620-I0NLGI provide for host system communication?

The P8620-I0NLGI provides three concurrent digital interfaces: SVID (for Intel SoC power negotiation), SPI (up to 8 MHz, master/slave) for configuration and telemetry readback, and I²C (up to 3.4 Mbps, slave-only) for secondary system management access. These interfaces allow simultaneous use - for example, SVID handles real-time voltage control while SPI reads current logs and I²C enables BMC-level monitoring - all supported natively by the P8620-I0NLGI.

Is the P8620-I0NLGI pinout fixed, or does it vary with firmware?

The physical pinout of the P8620-I0NLGI is fixed per its 64-QFN package and documented in R16DO0026EU0101 Rev.1.01; however, certain pin functions (e.g., GPIO roles, ADC input assignments) are firmware-configurable. While hardware-level signal routing is static, functional assignment - such as which GPIO acts as PMIC_EN or OVP control - depends on loaded firmware. Therefore, the P8620-I0NLGI pinout remains electrically consistent, but logical behavior requires matching firmware for intended platform operation.

P8620-I0NLGI Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Applications:: -

Current - Supply:: -

Voltage - Supply:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

P8620-I0NLGI FAQ

1.How can I place an order for P8620-I0NLGI through Aetrix?

Please submit a Request for Quotation (RFQ) for P8620-I0NLGI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for P8620-I0NLGI reliable?

The price and inventory of P8620-I0NLGI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for P8620-I0NLGI is usually 5 days.

3.What payment methods are accepted for P8620-I0NLGI?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for P8620-I0NLGI transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for P8620-I0NLGI?

P8620-I0NLGI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your P8620-I0NLGI order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for P8620-I0NLGI?

For technical support, including P8620-I0NLGI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your P8620-I0NLGI requirements.

6.How does Aetrix verify that P8620-I0NLGI is sourced from the original manufacturer or authorized distributors?

All P8620-I0NLGI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that P8620-I0NLGI meets industry standards.

7.What is the process for return or replacement of P8620-I0NLGI?

All P8620-I0NLGI units undergo pre-shipment inspection (PSI). If there is an issue with P8620-I0NLGI, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The P8620-I0NLGI part is unused and in its original packaging.

Return procedure for P8620-I0NLGI:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…