Nexperia USA Inc. PBSM5240PFH,115

Overview

PBSM5240PFH from Nexperia is a monolithic dual-die hybrid discrete device integrating a PNP low V_CEsat BISS transistor (−40 V, −2 A) and an N-channel Trench MOSFET (30 V, 0.66 A) in a single DFN2020-6 (SOT1118) package. It delivers ultra-low R_CEsat (240–340 mΩ) and R_DS(on) (370–580 mΩ), enabling high-efficiency load switching in space-constrained battery-powered systems.

For engineers reviewing the PBSM5240PFH datasheet, PBSM5240PFH pinout, PBSM5240PFH application, or PBSM5240PFH equivalent, this hybrid device supports compact power management designs requiring coordinated bipolar-MOS control, low thermal resistance (R_th(j-a) = 100–165 K/W), and validated safe operating area for motor/fan drive and charging circuits.

Technical Context

The device combines two independently controllable silicon dies: the PNP BISS transistor provides high-current, low-saturation switching with h_FE ≥75 at I_C = −1 A and V_CEsat ≤ −310 mV; the N-channel Trench MOSFET offers logic-level gate drive (V_GS(th) = 0.45–0.95 V), fast switching (t_d(on) = 4.0 ns), and robust 30 V drain-source breakdown.

Both dies share thermally optimized copper-exposed collector/drain pads on a common DFN2020-6 substrate, enabling simultaneous thermal management while maintaining electrical isolation-critical for bidirectional load control and fault-tolerant power path design.

Key Specifications

Pinout & Package

Package: DFN2020-6 (SOT1118), 2.0 × 2.0 × 0.65 mm, leadless, thermally enhanced, with exposed collector (pins 6 & 7) and drain (pins 3 & 8) pads for low R_th(j-a).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hybrid bipolar-MOS load switch applications.

Compared with DMN3026LSD-13 and discrete BC847B+PMV21ENEA, PBSM5240PFH uniquely integrates matched PNP/MOSFET characteristics in one thermally efficient package-enabling smaller footprints, lower conduction loss, and simplified control in dual-path power management.

Availability

PBSM5240PFH is available at Aetrix Electronics and suitable for battery-driven devices, charging circuits, and motor/fan power switches requiring stable component supply and guaranteed long-term manufacturability.

Supply support for PBSM5240PFH includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance, reliable discrete and logic devices for automotive, industrial, and consumer markets.

PBSM5240PFH belongs to Nexperia's BISS/Trench Hybrid portfolio, engineered specifically for space-constrained, high-efficiency power switching applications where thermal density and board area are primary constraints.

FAQ

What is the maximum continuous current the PBSM5240PFH can handle in a typical handheld PCB layout?

The PNP BISS transistor supports −1.8 A continuous collector current (I_C) and the N-channel MOSFET supports 0.66 A continuous drain current (I_D) at T_amb = 25 °C on FR4 with specified copper area. Derating applies above 25 °C ambient; at 60 °C, I_C drops to ~1.3 A and I_D to ~0.42 A per thermal curves in Figures 1–3 and 5–9 of the datasheet.

Can the PNP and MOSFET sections be driven simultaneously from the same microcontroller GPIO?

No-base (pin 2) and gate (pin 5) require independent drive signals. The PNP needs ~50 mA base current for full saturation at 500 mA collector load, while the MOSFET gate draws negligible steady-state current but requires ~0.89 nC total charge. Sharing one GPIO would cause unintended interaction and incomplete switching of either device.

Does PBSM5240PFH include internal ESD protection on all pins?

Yes-the device meets HBM ESD rating of ±2 kV (Class 2) per JESD22-A114, verified on all six terminals including emitter (pin 1), base (pin 2), drain (pins 3/8), source (pin 4), and gate (pin 5). No external ESD diodes are required for typical board-level handling per IEC 61000-4-2 Level 2.

Is the thermal pad on pins 6 and 7 electrically connected to the collector, and must it be soldered to PCB ground?

Pins 6 and 7 are the collector terminals and are electrically connected to each other and to the exposed thermal pad beneath the package. This pad must be soldered to a dedicated copper pour (≥6 cm² for PNP, ≥1 cm² for MOSFET per datasheet) but is not required to be grounded-it serves solely as a thermal conduction path and may float electrically per circuit requirements.