Nexperia USA Inc. PBSS5130PAP,115

Overview

PBSS5130PAP from Nexperia is a dual PNP low V_CEsat transistor in a DFN2020-6 (SOT1118) package, designed for high-efficiency load switching in space-constrained battery-powered systems. It delivers −30 V V_CEO, −1 A continuous I_C, 250 mΩ R_CEsat at −1 A/−0.1 A drive, and operates across −55 °C to +150 °C ambient. Used in portable power management and motor control circuits where thermal performance and PCB area are critical.

For engineers reviewing the PBSS5130PAP datasheet, PBSS5130PAP pinout, PBSS5130PAP application, or PBSS5130PAP equivalent, key selection criteria include verified dual-PNP topology, confirmed 250 mΩ saturation resistance under pulsed −1 A conditions, thermal resistance as low as 86 K/W on 4-layer PCB with collector pad, and documented pin mapping for TR1/TR2 emitter-base-collector assignment in SOT1118.

Technical Context

This device integrates two matched PNP transistors in a single leadless DFN2020-6 package, sharing no internal connection between channels-each transistor operates independently with separate emitter, base, and collector terminals. Its low saturation voltage is achieved via optimized epitaxial structure and emitter ballasting, enabling <175 mV V_CEsat at −1 A/−100 mA drive under pulsed conditions.

The dual configuration supports complementary switching topologies without cross-coupling, with individual absolute maximum ratings per transistor: −30 V V_CEO, −2 A I_CM, and −0.3 A I_B. Thermal performance is defined across eight mounting configurations, with junction-to-solder-point resistance fixed at 30 K/W regardless of PCB layout.

Key Specifications

Pinout & Package

DFN2020-6 (SOT1118) is a 2.0 mm × 2.0 mm × 0.65 mm leadless thermally enhanced plastic package with six exposed terminals on a single side. The bottom thermal pad is electrically connected to collector terminals C1 and C2, requiring solder mask-defined thermal land for optimal heat transfer.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-PNP switching applications.

Compared with PBSS4130PAN and DMN3028LSD-13, PBSS5130PAP uniquely delivers dual-PNP functionality in a 4 mm² footprint with guaranteed low V_CEsat without external bias networks-reducing BOM count and PCB area while maintaining compatibility with 3.3 V MCU GPIO drive.

Availability

PBSS5130PAP is available at Aetrix Electronics and suitable for portable power banks, USB-C PD accessories, medical wearables, and industrial sensor nodes requiring stable component supply and long-term manufacturability.

Supply support for PBSS5130PAP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential semiconductors, delivering high-performance, reliable components for automotive, industrial, mobile, and consumer markets.

PBSS5130PAP belongs to Nexperia's Low V_CEsat Transistor product line, engineered specifically for high-efficiency power switching in battery-constrained and thermally sensitive applications.

FAQ

What is the maximum allowable base current for continuous operation?

The absolute maximum base current (I_B) is −0.3 A per transistor, as specified in Table 5. For continuous DC operation at −1 A collector current, the recommended base drive is −100 mA to maintain 250 mΩ R_CEsat without thermal runaway. Exceeding −0.3 A risks metallization failure or bond wire degradation, especially above 85 °C ambient.

Can PBSS5130PAP be used in linear regulator pass-transistor applications?

No-PBSS5130PAP is characterized and qualified only for switching operation. Its Safe Operating Area (SOA) is not specified for linear mode, and thermal impedance data assumes pulsed or switched duty cycles. Linear use would exceed junction temperature limits due to uncontrolled power dissipation and lack of SOA derating curves.

Is the thermal pad electrically isolated or connected to a specific terminal?

The exposed thermal pad is electrically connected to both collector terminals (C1 and C2), as confirmed in the package outline and thermal test conditions. It must be soldered to a PCB copper pour tied to the system ground or power rail shared by both collectors-no isolation or floating connection is permitted for thermal or electrical integrity.

How does the device behave under mismatched base drive between TR1 and TR2?

TR1 and TR2 operate completely independently-applying base drive to only one transistor has no effect on the other's V_CEsat, leakage, or switching speed. This is verified by separate characterization in Table 7 and Fig. 10–17, which show identical per-transistor parameters under identical test conditions.