NXP Semiconductors PCA9460AUKZ
- Part No.:
- PCA9460AUKZ
- Manufacturer:
- NXP Semiconductors
- Category:
- Power Management - Specialized
- Package:
- 42-UFBGA, WLCSP
- Datasheet:
-
PCA9460AUKZ.pdf
- Description:
- POWER MANAGE IC (PMIC) FOR I.MX
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PCA9460AUKZ from NXP Semiconductors is a 13-channel power management IC (PMIC) engineered for ultra-low-power wearable and portable systems powered by the i.MX 8ULP processor. It integrates four buck regulators (including two with smart Dynamic Voltage Scaling), five LDOs (one 10 mA SNVS core LDO, three 250 mA PMOS LDOs, one 250 mA NMOS LDO), and four 150 mΩ load switches configurable as LED drivers - all operating with 1.5 µA quiescent current in low-power mode. It enables sub-100 µA system standby in eReaders, smartwatches, and handheld scanners.
For engineers reviewing the PCA9460AUKZ datasheet, PCA9460AUKZ pinout, PCA9460AUKZ application, or PCA9460AUKZ equivalent, this page delivers verified technical context, exact OTP-configured voltage defaults (BUCK1 = 1.8 V, BUCK2/BUCK3 = 1.0 V, BUCK4 = 1.1 V, LDO1 = 1.1 V, LDO2–LDO4 = 3.3 V/1.8 V), I²C-controlled DVS sequencing, and WL-CSP42 package constraints critical for i.MX 8ULP + LPDDR4 designs.
Technical Context
The PCA9460AUKZ implements a flexible OTP-programmed power sequencer supporting 16 PUD groups with configurable tON_STEP (2 ms) and tOFF_STEP (8 ms) timing, enabling precise startup/shutdown coordination across its 13 regulated rails. Its RUN-state operation supports three dynamic modes-ACTIVE, STANDBY, and DPSTANDBY-controlled via PMIC_STBY_REQ and STANDBY_CFG register bits, allowing selective rail retention during low-power states.
It features dual-mode reset architecture: WDOG_B and PMIC_RST_B support configurable warm reset (POR_B toggle only) or cold reset (full regulator recycle), while fault handling includes thermal shutdown (TJ ≥ TJSHDN → FAULT_SD → SNVS) and voltage regulator fault detection with 100 ms tFLT_SD_WAIT before forced shutdown - all managed through dedicated status and mask registers (INT1_STATUS, VRFLT1_MASK).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Regulators | Four 1 A synchronous buck converters: BUCK1 (1.8 V fixed), BUCK2 & BUCK3 (1.0 V DVS-capable), BUCK4 (1.1 V for LPDDR4) |
| LDOs | Five total: LDO_SNVS (3.0 V, 10 mA, always-on), LDO1 (1.1 V, 250 mA, NMOS), LDO2/LDO3 (3.3 V, 250 mA, PMOS), LDO4 (1.8 V, 250 mA, PMOS) |
| Quiescent Current | 1.5 µA in low-power mode; enables multi-week battery life in always-on wearables |
| I²C Interface | Fm+ (Fast-mode Plus) at 1 MHz; supports real-time DVS control and rail monitoring without CPU overhead |
| Load Switches | Four 150 mΩ Rdson switches with active discharge; configurable as LED drivers with two blink patterns |
| Package | WLCSP42 (2.86 mm × 2.46 mm, 0.4 mm pitch); optimized for space-constrained wearable PCBs |
| OTP Configuration | PCA9460A variant: pre-programmed for i.MX 8ULP + LPDDR4; fixed BUCK4 = 1.1 V, LDO1 = 1.1 V, power-up sequence per Table 5 |
Pinout & Package
PCA9460AUKZ uses a 42-bump wafer-level chip-scale package (WLCSP42), measuring 2.86 mm × 2.46 mm with 0.4 mm pitch and 0.525 mm body height (backside coating included). The bump-side-down top view defines pin positions A1–G6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MODE0–MODE2 | Digital input | Selects power state transitions (RUN/STANDBY/DPSTANDBY) and enables hardware-based sequencing control |
| PMIC_ON_REQ / PMIC_STBY_REQ | Digital input | Initiates full power-up sequence or enters low-power standby mode; debounced and OR'd with ACOK_B/PMIC_RST_B |
| BUCK1FB–BUCK4FB | Analog input | Resistor-divider feedback nodes for closed-loop output voltage regulation; sets BUCK1 = 1.8 V, BUCK2/3 = 1.0 V, BUCK4 = 1.1 V |
| LDO1–LDO4 / LDO_SNVS | Power output | Regulated outputs: LDO1 (1.1 V), LDO2/LDO3 (3.3 V), LDO4 (1.8 V), LDO_SNVS (3.0 V); each with built-in active discharge |
| LSW1IN–LSW4IN / LSW1OUT–LSW4OUT | Power switch I/O | Four independent load switch channels; IN pins accept VSYS input, OUT pins drive peripherals or LEDs with current-source capability |
| SCL / SDA | I²C interface | Fm+ 1 MHz bidirectional bus for runtime configuration, status readback, and DVS voltage updates |
| POR_B | Open-drain output | Power-on reset signal asserted low during startup and reset events; requires external pull-up resistor |
Key Features
| Feature | Design Value |
|---|---|
| Smart DVS Control | Two buck regulators (BUCK2, BUCK3) support 12.5 mV/step voltage scaling at 25 mV/2 µs speed for i.MX 8ULP core voltage optimization |
| Ultra-Low Standby Power | 1.5 µA quiescent current in low-power mode reduces system leakage, extending battery life in always-on wearables |
| Configurable LED Driver | Four load switches support dual-pattern blinking (e.g., heartbeat + alert) without external components or MCU GPIO overhead |
| OTP-Powered Sequencing | Fixed power-up order (T1–T16 groups) pre-programmed in on-chip OTP memory eliminates need for external sequencer or firmware initialization |
| Thermal & Fault Protection | Automatic transition to FAULT_SD state on thermal shutdown (TJ ≥ TJSHDN) or unmasked VR fault, followed by safe return to SNVS |
Applications
| eReader Power Management | Smartwatch Core Supply |
|---|---|
|
Use Scenario: E-ink display device requiring weeks of battery life with intermittent wake-up for page turns and wireless sync. IC Role / Device Role / Timing Role: Primary PMIC delivering regulated rails to i.MX 8ULP SoC, LPDDR4 memory, and display interface; manages deep-sleep entry/exit via PMIC_STBY_REQ. Use Value: 1.5 µA quiescent current and OTP-locked sequencing minimize standby drain while ensuring reliable cold-start from coin-cell or small Li-ion. |
Use Scenario: Compact wrist-worn device with always-on sensor hub, Bluetooth LE radio, and optical heart-rate monitor. IC Role / Device Role / Timing Role: Central power controller supplying 1.1 V to Cortex-M7 core, 3.3 V to BLE transceiver, 1.8 V to sensors, and 3.0 V to secure non-volatile storage (SNVS). Use Value: Integrated LDO_SNVS (3.0 V, 10 mA) and active discharge resistors ensure deterministic power-down behavior and fast rail collapse during mode transitions. |
| Handheld Scanner Power System | Portable Headset Audio Supply |
|
Use Scenario: Battery-powered barcode scanner with laser diode, CMOS imager, and USB-C charging interface. IC Role / Device Role / Timing Role: Single-chip solution providing 1.8 V for image sensor, 1.0 V DVS rails for processor DVFS, and load-switched 5 V boost for laser driver enable. Use Value: Four 150 mΩ load switches replace discrete MOSFETs; configurable as current sources for LED indicators or laser bias control. |
Use Scenario: Wireless stereo headset with ANC, touch controls, and voice assistant activation. IC Role / Device Role / Timing Role: Supplies 1.1 V to DSP core, 3.3 V to codec and Bluetooth radio, and drives RGB status LEDs via LSW1–LSW4 with programmable blink patterns. Use Value: Dual-blink LED driver mode eliminates need for external timer IC or firmware-driven PWM, reducing BOM count and firmware complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PCA9460BUKZ | Same WLCSP42 package and pinout; OTP-configured for i.MX 8ULP + LPDDR4X (BUCK4 = 1.1 V, LDO1 = 0.6 V) | Targeted at higher-bandwidth memory interfaces; not drop-in for LPDDR4 systems due to different default LDO1 voltage | Select PCA9460BUKZ only when migrating to LPDDR4X memory; verify LDO1 voltage compatibility with SoC core logic |
| PCA9460CUKZ | Same footprint and pinout; OTP-set for i.MX 8ULP + LPDDR3 (BUCK4 = 1.2 V, LDO1 = 1.2 V) | Designed for legacy LPDDR3 platforms; incompatible with LPDDR4 voltage requirements and sequencing defaults | Use PCA9460CUKZ exclusively for LPDDR3-based i.MX 8ULP designs; avoid in LPDDR4 systems due to BUCK4/LDO1 mismatch |
Compared with PCA9460BUKZ and PCA9460CUKZ, the PCA9460AUKZ provides the only OTP-matched configuration for i.MX 8ULP + LPDDR4 - ensuring correct BUCK4 (1.1 V), LDO1 (1.1 V), and power-up group timing without register reprogramming or layout changes.
Availability
PCA9460AUKZ is available at Aetrix Electronics and suitable for ultra-low-power portable devices, wearable electronics, and i.MX 8ULP-based embedded systems requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for PCA9460AUKZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ARM-based application processors and integrated power management.
The PCA9460 series is part of NXP's i.MX 8ULP ecosystem, designed specifically to deliver ultra-low-quiescent-power, OTP-configured power sequencing and DVS control for battery-constrained edge devices running NXP's ultra-low-power application processors.
FAQ
What is the default output voltage of BUCK4 on the PCA9460AUKZ?
The PCA9460AUKZ is an OTP-configured variant for i.MX 8ULP + LPDDR4, and its BUCK4 output is factory-set to 1.1 V. This matches the standard VDDQ requirement for LPDDR4 memory interfaces and cannot be altered without OTP reprogramming - which is not supported in the field. Always verify BUCK4 voltage with a multimeter during bring-up, especially if using custom feedback resistors.
Does the PCA9460AUKZ support dynamic voltage scaling (DVS) on all buck regulators?
No - only BUCK2 and BUCK3 support smart DVS on the PCA9460AUKZ, with 12.5 mV/step resolution and 25 mV/2 µs slew rate. BUCK1 is fixed at 1.8 V for i.MX 8ULP core I/O, and BUCK4 is fixed at 1.1 V for LPDDR4. DVS control is implemented via I²C writes to BUCK2OUT_DVS0/BUCK3OUT_DVS0 registers and enabled by default in OTP configuration.
How does the PCA9460AUKZ handle power loss on the VSYS rail?
The PCA9460AUKZ monitors VSYS for undervoltage lockout (UVLO) at 2.85 V. When VSYS falls below this threshold, it immediately enters OFF state, turning off all regulators including LDO_SNVS and resetting internal registers. An errata (ES_PCA9460 Rev. 1.0) documents improper power-up behavior if residual voltage remains on VSYS during restart - a hardware workaround using a VSYS discharge FET is recommended for robust recovery.
Can the PCA9460AUKZ load switches be used as constant-current LED drivers?
Yes - all four load switches (LSW1–LSW4) on the PCA9460AUKZ can be configured as current-source LED drivers with two programmable blink patterns via I²C. Each switch supports up to 20 mA sink current with internal current-setting; LSW1OUT–LSW4OUT become current-source outputs when LED mode is enabled, eliminating external current-limiting resistors for status indicators.
What is the purpose of the LDO_SNVS output on the PCA9460AUKZ?
The LDO_SNVS pin on the PCA9460AUKZ delivers a fixed 3.0 V, 10 mA output dedicated to powering the i.MX 8ULP's Secure Non-Volatile Storage (SNVS) domain. It powers real-time clocks, tamper-detection circuitry, and cryptographic key storage - and remains active even during deep standby (DPSTANDBY) mode, ensuring timekeeping and security state persistence across sleep cycles.
PCA9460AUKZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 42-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Microcontroller, MCU
- Current - Supply:
- -
- Voltage - Supply:
- 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 42-WLCSP (2.86x2.46)
PCA9460AUKZ FAQ
1.How can I place an order for PCA9460AUKZ through Aetrix?
Please submit a Request for Quotation (RFQ) for PCA9460AUKZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PCA9460AUKZ reliable?
The price and inventory of PCA9460AUKZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PCA9460AUKZ is usually 5 days.
3.What payment methods are accepted for PCA9460AUKZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PCA9460AUKZ transactions.
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4.How is shipping managed for PCA9460AUKZ?
PCA9460AUKZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PCA9460AUKZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PCA9460AUKZ?
For technical support, including PCA9460AUKZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PCA9460AUKZ requirements.
6.How does Aetrix verify that PCA9460AUKZ is sourced from the original manufacturer or authorized distributors?
All PCA9460AUKZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PCA9460AUKZ meets industry standards.
7.What is the process for return or replacement of PCA9460AUKZ?
All PCA9460AUKZ units undergo pre-shipment inspection (PSI). If there is an issue with PCA9460AUKZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PCA9460AUKZ part is unused and in its original packaging.
Return procedure for PCA9460AUKZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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