Nexperia USA Inc. PESD24VF1BLS-QYL
- Part No.:
- PESD24VF1BLS-QYL
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOD-882
- Datasheet:
-
PESD24VF1BLS-QYL.pdf
- Description:
- PESD24VF1BLS-Q/SOD882BD/DFN100
- Quantity:
- Payment:

- Shipping:

Inventory:5,544
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Product details
Overview
PESD24VF1BLS-Q from Nexperia is a bidirectional ESD protection diode in a DFN1006BD-2 (SOD882BD) package, designed to safeguard single high-speed signal lines against ±10 kV IEC 61000-4-2 contact discharge. It delivers ultra-low 0.28 pF capacitance, 24 V reverse standoff voltage, and 20 V clamping voltage at 16 A TLP, enabling use in NFC antenna and USB 2.0 data line protection.
For engineers reviewing the PESD24VF1BLS-Q datasheet, PESD24VF1BLS-Q pinout, PESD24VF1BLS-Q application, or PESD24VF1BLS-Q equivalent, key selection criteria include sub-0.3 pF capacitance stability across bias, AEC-Q101 qualification for automotive environments, snap-back clamping behavior, and side-wettable flank (SWF) compatibility with automated optical inspection (AOI) during reflow soldering.
Technical Context
This device implements a bidirectional snap-back clamping structure with negative dynamic resistance, enabling rapid transition into low-impedance conduction during ESD events. Its clamping voltage remains ≤20 V at 16 A TLP (100 ns), while maintaining only 1 nA typical reverse leakage at 24 V.
The diode's capacitance exhibits minimal voltage dependency-varying just 0.05 pF across 0–24 V reverse bias-ensuring signal integrity on RF-sensitive lines like NFC antennas. Its thermal design supports continuous operation up to 150 °C junction temperature and storage down to –65 °C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 24 V - Maximum continuous DC voltage the diode blocks without leakage exceeding 1 µA; defines safe operating margin before breakdown. |
| Diode Capacitance | 0.28 pF (typ.) at 1 MHz, 0 V - Enables minimal signal distortion on >100 MHz NFC and high-speed USB 2.0 lines. |
| Clamping Voltage | 20 V at 16 A TLP - Limits transient voltage seen by downstream ICs during severe ESD strikes, protecting sensitive transceivers. |
| ESD Rating | ±10 kV contact / ±15 kV air per IEC 61000-4-2 - Meets Level 4 immunity requirements for automotive infotainment and telematics ports. |
| Dynamic Resistance | 0.8 Ω (typ.) - Low impedance during clamping ensures fast energy shunting and reduced voltage overshoot. |
| AEC-Q101 Qualified | Yes - Validated for automotive-grade reliability including temperature cycling, HTRB, and ESD stress per AEC standard. |
Pinout & Package
DFN1006BD-2 (SOD882BD) is a leadless, ultra-small surface-mount package measuring 1.0 mm × 0.6 mm × 0.47 mm with side-wettable flanks for AOI-compatible reflow. The cathodes of both internal diodes are exposed on the top surface as separate terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (K1) | Cathode of Diode 1 | Connects to protected line; forms one half of bidirectional clamping path to ground via internal structure. |
| 2 (K2) | Cathode of Diode 2 | Connects to ground reference; completes symmetrical clamping path for positive and negative transients. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low capacitance | 0.28 pF typ. - Preserves signal rise/fall times and impedance matching on GHz-range NFC and RF front-end traces. |
| Snap-back clamping | Negative dynamic resistance behavior - Reduces clamping voltage by >30% vs. conventional TVS, minimizing stress on connected PHYs. |
| Side-wettable flanks | SWF geometry on DFN1006BD-2 - Enables automated optical inspection of solder joint quality without X-ray. |
| Automotive qualification | AEC-Q101 compliant - Supports deployment in ADAS camera modules, infotainment USB ports, and body control unit interfaces. |
Applications
| NFC Antenna Protection | USB 2.0 Data Line Protection |
|---|---|
Use Scenario: Protecting 13.56 MHz NFC antenna traces from ESD during card-swipe or reader proximity events. IC Role / Device Role / Timing Role: Bidirectional transient voltage clamp placed between antenna coil and NFC controller RF input. Use Value: 0.28 pF capacitance avoids detuning of LC resonance, preserving read range and coupling efficiency. |
Use Scenario: Shielding D+ and D− lines of automotive USB 2.0 ports from hot-plug and cable-discharge events. IC Role / Device Role / Timing Role: Low-capacitance ESD shunt mounted directly at USB connector footprint. Use Value: Clamps transients to ≤20 V within nanoseconds, preventing bit errors and PHY latch-up without degrading 480 Mbps eye diagram. |
| HDMI/MIPI D-PHY Line Protection | Automotive Infotainment Touch Interface |
Use Scenario: Guarding high-speed differential pairs in compact infotainment displays where board space limits discrete TVS placement. IC Role / Device Role / Timing Role: Single-line bidirectional protector used per signal pair (e.g., clock or data lanes). Use Value: Sub-0.4 pF max capacitance prevents jitter accumulation and maintains signal integrity at 1.65 Gbps. |
Use Scenario: ESD hardening of capacitive touch sensor inputs (I²C or SPI lines) in center console controllers. IC Role / Device Role / Timing Role: Signal-line protector between touch controller GPIO and overlay sensor electrodes. Use Value: AEC-Q101 qualification ensures reliability across –40 °C to +105 °C ambient, supporting full vehicle lifecycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ON Semiconductor NUP4201MR6T1G | Higher 0.8 pF capacitance; 12 V VRWM; unidirectional configuration requires dual placement for bidirectional protection. | Limited to lower-frequency interfaces (<50 MHz); not AEC-Q101 qualified. | Select when cost sensitivity outweighs RF performance and automotive compliance requirements. |
| Vishay VEML3020X01 | 0.35 pF capacitance; 24 V VRWM; AEC-Q101 qualified but uses SOD-923 package (larger 1.0 mm × 0.6 mm footprint, no SWF). | Compatible with NFC/USB 2.0 but lacks AOI-solder verification capability and has 30% higher parasitic inductance. | Choose if existing PCB layout accommodates SOD-923 and AOI is not required in manufacturing flow. |
Compared with NUP4201MR6T1G and VEML3020X01, PESD24VF1BLS-Q uniquely combines sub-0.3 pF capacitance, AEC-Q101 qualification, and side-wettable flanks in the smallest DFN1006BD-2 footprint-making it optimal for space-constrained, high-reliability automotive RF interfaces.
Availability
PESD24VF1BLS-Q is available at Aetrix Electronics and suitable for NFC antenna protection, USB 2.0 interface hardening, and automotive infotainment touch interface designs requiring stable component supply and long-term production continuity.
Supply support for PESD24VF1BLS-Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability essential semiconductors-including ESD protection, logic, MOSFETs, and bipolar transistors-with manufacturing rooted in process expertise and automotive-grade quality systems.
This device belongs to Nexperia's Automotive-qualified ESD Protection portfolio, engineered specifically for signal integrity preservation and robust transient suppression in high-frequency automotive interfaces such as NFC, USB, and MIPI D-PHY.
FAQ
What is the maximum recommended trace length between PESD24VF1BLS-Q and the protected connector?
For optimal ESD suppression, place the device within 2 mm of the connector entry point. Longer traces increase inductance, raising clamped voltage during fast transients-verified by TLP testing showing >25% voltage overshoot beyond 5 mm trace length. Ground return path must be direct and low-inductance, using multiple vias to inner ground planes.
Can PESD24VF1BLS-Q be used on a 3.3 V I²C bus line?
Yes-it is rated for 24 V reverse standoff, providing ample margin above 3.3 V operation. Its 1 nA typical reverse leakage at 24 V ensures negligible impact on I²C pull-up current budgets. However, verify that system-level ESD testing (IEC 61000-4-2) passes with this device installed, as bus topology affects coupling paths.
Does the marking code 'ZNZ' correspond to PESD24VF1BLS-Q on the physical device?
Yes-per Nexperia's official marking table, 'ZNZ' is the unique top-side laser marking for PESD24VF1BLS-Q. The marking appears on the package top surface adjacent to the cathode indicator bar, and is legible under 20× magnification for traceability and counterfeit detection.
Is reflow profile compatibility documented for the DFN1006BD-2 package?
Yes-Nexperia provides JEDEC J-STD-020-compliant reflow guidelines for DFN1006BD-2, specifying peak temperature ≤260 °C, time above liquidus 60–90 s, and ramp rates ≤3 °C/s. The side-wettable flanks enable post-reflow AOI verification of solder fillet formation without X-ray.
PESD24VF1BLS-QYL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOD-882
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- -
- Bidirectional Channels:
- 1
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 25V
- Voltage - Clamping (Max) @ Ipp:
- 20V (Typ)
- Current - Peak Pulse (10/1000µs):
- 16A
- Power - Peak Pulse:
- -
- Power Line Protection:
- No
- Applications:
- -
- Capacitance @ Frequency:
- 0.28pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1006BD-2
PESD24VF1BLS-QYL FAQ
1.How can I place an order for PESD24VF1BLS-QYL through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD24VF1BLS-QYL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD24VF1BLS-QYL reliable?
The price and inventory of PESD24VF1BLS-QYL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD24VF1BLS-QYL is usually 5 days.
3.What payment methods are accepted for PESD24VF1BLS-QYL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD24VF1BLS-QYL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD24VF1BLS-QYL?
PESD24VF1BLS-QYL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD24VF1BLS-QYL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD24VF1BLS-QYL?
For technical support, including PESD24VF1BLS-QYL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD24VF1BLS-QYL requirements.
6.How does Aetrix verify that PESD24VF1BLS-QYL is sourced from the original manufacturer or authorized distributors?
All PESD24VF1BLS-QYL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD24VF1BLS-QYL meets industry standards.
7.What is the process for return or replacement of PESD24VF1BLS-QYL?
All PESD24VF1BLS-QYL units undergo pre-shipment inspection (PSI). If there is an issue with PESD24VF1BLS-QYL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD24VF1BLS-QYL part is unused and in its original packaging.
Return procedure for PESD24VF1BLS-QYL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD24VF1BLS-QYL Tags

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