Nexperia USA Inc. PESD24VS1UL-QZ
- Part No.:
- PESD24VS1UL-QZ
- Manufacturer:
- Nexperia USA Inc.
- Category:
- TVS Diodes
- Package:
- SOD-882
- Datasheet:
-
PESD24VS1UL-QZ.pdf
- Description:
- PESD24VS1UL-Q/SOD882/DFN1006-2
- Quantity:
- Payment:

- Shipping:

Inventory:8,710
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Product details
Overview
PESD24VS1UL-Q from Nexperia is a unidirectional ESD protection diode in a DFN1006-2 (SOD882) package, designed to safeguard single high-speed signal lines against electrostatic discharge and surge transients. It delivers 24 V reverse standoff voltage, 23 pF typical capacitance at 1 MHz, 23 kV IEC 61000-4-2 contact discharge rating, 150 W peak pulse power, and 1 nA reverse leakage - deployed in automotive infotainment data interfaces.
For engineers reviewing the PESD24VS1UL-Q datasheet, PESD24VS1UL-Q pinout, PESD24VS1UL-Q application, or PESD24VS1UL-Q equivalent, key selection criteria include clamping voltage under 3 A surge (70 V), ultra-low capacitance for USB 2.0/MIPI compatibility, AEC-Q101 qualification, and cathode-marked leadless SMD placement near connectors.
Technical Context
This device operates as a unidirectional transient voltage suppressor with avalanche breakdown at 26.5–27.5 V and clamps transients to ≤70 V at 3 A (8/20 µs). Its low 23 pF capacitance ensures minimal signal distortion on high-speed lines up to 480 Mbps.
The DFN1006-2 package enables PCB-level ESD protection with minimal parasitic inductance, while the cathode-anode terminal configuration supports polarity-specific line protection where signal swings only positive or negative relative to ground.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Reverse Standoff Voltage | 24 V - Maximum continuous operating voltage before conduction begins; defines safe signal swing range. |
| Clamping Voltage | 70 V at 3 A (8/20 µs) - Peak voltage seen by protected IC during worst-case surge; limits stress on downstream components. |
| Diode Capacitance | 23 pF (typ.) at 1 MHz - Enables use on USB 2.0, HDMI DDC, MIPI D-PHY, and other <500 Mbps interfaces without signal integrity loss. |
| ESD Rating | 23 kV contact discharge (IEC 61000-4-2 Level 4) - Meets highest industrial and automotive ESD immunity requirements. |
| Peak Pulse Power | 150 W - Sustains short-duration surges per IEC 61000-4-5 without degradation. |
| Reverse Leakage | 1 nA at 24 V - Negligible DC loading on bias-sensitive analog or reference lines. |
Pinout & Package
DFN1006-2 (SOD882) plastic leadless package: 1.0 mm × 0.6 mm × 0.48 mm body, 0.65 mm pitch, 2-terminal surface-mount design with exposed thermal pad not present. Marking bar indicates cathode.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (K) | Cathode | Connected to protected signal line; conducts during positive transients when line voltage exceeds VRWM + VBR. |
| 2 (A) | Anode | Connected to system ground; completes current path during ESD events, enabling low-impedance transient shunting. |
Key Features
| Feature | Design Value |
|---|---|
| AEC-Q101 qualified | Validated for automotive-grade reliability including temperature cycling, HTRB, and ESD stress - suitable for ADAS camera links and infotainment buses. |
| Ultra-low 23 pF capacitance | Preserves signal rise/fall times on high-speed differential pairs; avoids jitter and bit errors in USB 2.0 and LVDS applications. |
| 1 nA reverse leakage | Prevents DC offset accumulation in precision sensor front-ends and reference voltage monitoring paths. |
| 70 V clamping at 3 A | Protects 3.3 V and 5 V logic interfaces (e.g., UART, I²C, CAN FD physical layer) from damage during 8/20 µs surge events. |
Applications
| Automotive Infotainment Interfaces | USB 2.0 Data Lines |
|---|---|
Use Scenario: Protecting MIPI D-PHY lanes between head unit SoC and display module in vehicles exposed to ISO 10605 ESD events. IC Role / Device Role / Timing Role: Unidirectional clamping diode placed within 3 mm of connector to limit transient overshoot on 800 Mbps differential signals. Use Value: Prevents latch-up or gate oxide rupture in display driver ICs while maintaining eye diagram integrity via 23 pF capacitance. |
Use Scenario: ESD protection on USB 2.0 D+ and D− lines in portable medical devices requiring IEC 60601-1-2 compliance. IC Role / Device Role / Timing Role: Single-line protector mounted adjacent to USB receptacle to clamp ±8 kV contact discharges per IEC 61000-4-2. Use Value: Ensures full-speed USB enumeration remains functional after repeated ESD strikes due to 23 kV rating and sub-70 V clamping. |
| Industrial Sensor Signal Conditioning | Audio Line Inputs (TRS) |
Use Scenario: Shielding analog output lines from pressure and temperature sensors in factory automation PLC I/O modules. IC Role / Device Role / Timing Role: Reverse-biased protection element on 0–10 V or 4–20 mA output paths subject to cable discharge events. Use Value: Maintains <1 nA leakage to avoid calibration drift while suppressing >1 kV transients induced by relay switching noise. |
Use Scenario: Protecting balanced/unbalanced audio inputs on professional mixing consoles handling AES3 or analog TRS jacks. IC Role / Device Role / Timing Role: Cathode-to-signal, anode-to-ground configuration on left/right channel lines to suppress human-body-model ESD. Use Value: Eliminates pop/noise artifacts during connector hot-plug by clamping transients below amplifier input damage threshold. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar unidirectional ESD protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ESD9X3.3SFT5G | 3.3 V VRWM, 12 pF capacitance, 12 kV ESD rating, SOD-923 package | Better suited for low-voltage I/O (1.8–3.3 V), but insufficient for 24 V signal rails | Select only for sub-5 V logic; not interchangeable due to lower standoff voltage. |
| TPD2E001DRYR | Dual-channel, 5.5 V VRWM, 12 pF per channel, 8 kV IEC 61000-4-2, SOT-553 | Offers dual-line protection in same footprint, but lower ESD rating and higher leakage (5 nA) | Choose when protecting two adjacent lines (e.g., I²C SDA/SCL); not a drop-in replacement for single-line 24 V use. |
Compared with ESD9X3.3SFT5G and TPD2E001DRYR, PESD24VS1UL-Q uniquely supports 24 V signal environments with automotive-grade robustness and lowest trade-off between capacitance and ESD rating in its class.
Availability
PESD24VS1UL-Q is available at Aetrix Electronics and suitable for automotive infotainment interfaces, USB 2.0 data lines, and industrial sensor signal conditioning requiring stable component supply across production lifecycles.
Supply support for PESD24VS1UL-Q includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, headquartered in Nijmegen, Netherlands.
This device belongs to Nexperia's Automotive ESD Protection portfolio, engineered specifically for AEC-Q101-compliant transient suppression in harsh-temperature, high-reliability signal paths such as camera links and body control modules.
FAQ
What is the maximum operating temperature for PESD24VS1UL-Q?
The junction temperature must not exceed 150 °C, and the ambient operating range is −55 °C to +150 °C. Derating applies above 85 °C ambient per Figure 4 in the datasheet, where peak pulse power drops to ~80% at 125 °C junction temperature.
Can PESD24VS1UL-Q protect bidirectional signal lines?
No - it is strictly unidirectional and only clamps positive transients on the cathode-connected line. For bidirectional protection (e.g., USB D+/D−), two devices back-to-back or a dedicated bidirectional part like PESD5V0S1BA is required.
How does the marking "G5" relate to the device identity?
"G5" is the top-side laser marking code for PESD24VS1UL-Q per Table 4; it uniquely identifies this variant in the SOD882 package and distinguishes it from other PESD-series parts like PESD5V0S1UL (marked "G3").
Is PCB layout critical for achieving rated ESD performance?
Yes - layout directly impacts clamping effectiveness. The datasheet mandates placement within 3 mm of the protected connector, shortest possible trace length to ground, and avoidance of shared return paths; failure to follow these reduces effective ESD immunity by up to 40%.
PESD24VS1UL-QZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Package/Case:
- SOD-882
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Zener
- Unidirectional Channels:
- 1
- Bidirectional Channels:
- -
- Voltage - Reverse Standoff (Typ):
- 24V (Max)
- Voltage - Breakdown (Min):
- 26.5V
- Voltage - Clamping (Max) @ Ipp:
- 70V
- Current - Peak Pulse (10/1000µs):
- 3A (8/20µs)
- Power - Peak Pulse:
- 150W
- Power Line Protection:
- No
- Applications:
- Telecom
- Capacitance @ Frequency:
- 23pF @ 1MHz
- Operating Temperature:
- -55°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q101
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1006-2
PESD24VS1UL-QZ FAQ
1.How can I place an order for PESD24VS1UL-QZ through Aetrix?
Please submit a Request for Quotation (RFQ) for PESD24VS1UL-QZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PESD24VS1UL-QZ reliable?
The price and inventory of PESD24VS1UL-QZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PESD24VS1UL-QZ is usually 5 days.
3.What payment methods are accepted for PESD24VS1UL-QZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PESD24VS1UL-QZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PESD24VS1UL-QZ?
PESD24VS1UL-QZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PESD24VS1UL-QZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PESD24VS1UL-QZ?
For technical support, including PESD24VS1UL-QZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PESD24VS1UL-QZ requirements.
6.How does Aetrix verify that PESD24VS1UL-QZ is sourced from the original manufacturer or authorized distributors?
All PESD24VS1UL-QZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PESD24VS1UL-QZ meets industry standards.
7.What is the process for return or replacement of PESD24VS1UL-QZ?
All PESD24VS1UL-QZ units undergo pre-shipment inspection (PSI). If there is an issue with PESD24VS1UL-QZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PESD24VS1UL-QZ part is unused and in its original packaging.
Return procedure for PESD24VS1UL-QZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PESD24VS1UL-QZ Tags

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Nexperia USA Inc.

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