Microchip Technology PM6108B-FEI

Overview

PM6108B-FEI from Microchip Technology is a 48-channel multi-rate Ethernet MAC/PHY IC supporting 1 GE to 400 GE client rates, 1.2 Tbps aggregate capacity with PAM4 SerDes, line-speed MACsec encryption, and IEEE 1588v2 Class C/D timestamping for 5G transport infrastructure.

For engineers reviewing the PM6108B-FEI datasheet, PM6108B-FEI pinout, PM6108B-FEI application, or PM6108B-FEI equivalent, key selection criteria include SerDes count (48), retiming/gearboxing capability, FlexE support, PTP accuracy class, and MACsec engine integration in a single die.

Technical Context

The PM6108B-FEI implements dual-domain SerDes architecture: 24 host-side and 24 line-side channels, each configurable as NRZ (up to 28 Gbps) or PAM4 (up to 56 Gbps). It supports analog and PCS-level retiming, forward/reverse gearboxing (800 Gbps mode), and hitless 2:1 mux for working/protect switching.

It integrates hardware-accelerated MACsec (AES-256-GCM) operating at line rate, full FlexE 2.1 sublayer support including calendar-based multiplexing, and crosspoint switching enabling any-to-any SerDes interconnection without external fabric.

Key Specifications

Pinout & Package

PM6108B-FEI is housed in a 27 mm × 27 mm, 1156-pin FC-BGA package with controlled impedance routing for high-speed SerDes lanes. Pin assignment follows Microchip's META-DX1 family layout standard, with dedicated banks for host SerDes (pins A1–H20), line SerDes (pins R1–Y20), power/ground (distributed across perimeter), and management interfaces (I²C, JTAG, MDIO).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet MAC/PHY applications.

Compared with PM6110B-FEI and PM6104B-FEI, the PM6108B-FEI delivers the optimal balance of security (MACsec), flexibility (FlexE), and timing precision (Class C/D PTP) without over-provisioning Interlaken or under-provisioning encryption-making it the default choice for next-gen DCI and 5G transport line cards.

Availability

PM6108B-FEI is available at Aetrix Electronics and suitable for high-density router line cards, encryption appliances, FlexE-based DCI muxponders, and working/protect transport switches requiring stable component supply across multi-year production cycles.

Supply support for PM6108B-FEI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a global provider of microcontroller, analog, FPGA, and connectivity solutions, with leadership in timing, security, and communications ICs.

The META-DX1 product line was designed specifically for high-capacity Ethernet infrastructure-enabling 5G transport, hyperscale DCI, and carrier-grade working/protect switching through integrated MAC/PHY, MACsec, FlexE, and precision timing.

FAQ

What Ethernet data rates does the PM6108B-FEI support?

The PM6108B-FEI supports client Ethernet rates from 1 GE to 400 GE per channel, with full line-rate operation across all rates. It achieves this using 48 programmable SerDes lanes-each configurable as 28 Gbps NRZ or 56 Gbps PAM4-and includes built-in gearboxing to bridge rate mismatches, such as mapping four 100G clients onto a single 400G line interface. The PM6108B-FEI does not require external rate adaptation logic.

Does the PM6108B-FEI include hardware-accelerated MACsec encryption?

Yes, the PM6108B-FEI integrates dedicated hardware MACsec engines compliant with IEEE 802.1AE-2018, supporting AES-256-GCM encryption and decryption at full line rate up to 400 GE per port. All frames-including pause, control, and management frames-are secured without packet buffering or CPU involvement. The PM6108B-FEI enables end-to-end WAN security without performance penalty or added latency.

What level of IEEE 1588v2 timestamping accuracy does the PM6108B-FEI provide?

The PM6108B-FEI delivers IEEE 1588v2 Class C/D-compliant timestamping with hardware-assisted ingress/egress capture and correction, achieving sub-10 ns synchronization uncertainty under typical operating conditions. This meets the strict timing requirements of 5G fronthaul and mobile backhaul networks. The PM6108B-FEI also supports SyncE for frequency synchronization alongside PTP for phase alignment.

Can the PM6108B-FEI be used in FlexE-based data center interconnect applications?

Yes, the PM6108B-FEI implements the full FlexE 2.1 sublayer, including calendar-based multiplexing, group management, and client isolation. It enables efficient aggregation of sub-100G clients (e.g., 10/25/40/50 GE) onto higher-rate interfaces (100G/200G/400G) without LAG overhead. The PM6108B-FEI is deployed in hyperscale DCI muxponders where FlexE simplifies bandwidth provisioning and improves spectral efficiency.

What is the SerDes configuration and packaging of the PM6108B-FEI?

The PM6108B-FEI features 48 high-speed SerDes lanes-24 host-side and 24 line-side-each supporting both NRZ (up to 28 Gbps) and PAM4 (up to 56 Gbps) signaling. It is packaged in a 27 mm × 27 mm, 1156-pin flip-chip ball grid array (FC-BGA) with thermal lid and controlled impedance routing optimized for 56G PAM4 channel integrity. The PM6108B-FEI requires precise PCB stack-up and reference plane design per Microchip's layout guidelines.