STMicroelectronics PM6670AS

Overview

PM6670AS from STMicroelectronics is a complete DDR2/3 memory power supply controller integrating a constant-on-time (COT) buck controller for VDDQ, a 2 A sink/source LDO for VTT termination, and a ±15 mA low-noise buffered VTTREF. It delivers fixed 1.8 V (DDR2) or 1.5 V (DDR3) VDDQ outputs with ±1% accuracy, supports ceramic output capacitors, and enables S3/S4/S5 system sleep-state compliance. Used in DDR memory subsystems of digital TVs and embedded computing platforms.

For engineers reviewing the PM6670AS datasheet, PM6670AS pinout, PM6670AS application, or PM6670AS equivalent, key selection criteria include its dual-mode COT control architecture, R_DS(ON)-based current sensing, negative current limit capability, non-tracking VDDQ discharge, and multilevel MODE/DDRSEL logic for DDR voltage and pulse-skip mode selection.

Technical Context

The PM6670AS implements a constant-on-time (COT) PWM control loop for the VDDQ buck stage, using VSNS for remote output sensing and COMP for DC error compensation via an embedded integrator that cancels ripple-induced DC offset. Its gate drivers feature anti-cross-conduction logic, 0.6–2.7 Ω on-resistance, and bootstrap (BOOT) biasing for high-side drive.

The VTT section integrates a foldback-limited 2 A linear regulator with VTTSNS remote sensing, high-Z output in S3 state, and tracking discharge behavior when LDOIN = VDDQ. The VTTREF buffer delivers 0.9 V (DDR2) or 0.75 V (DDR3) referenced to VSNS/2 with ±2% accuracy and 15 mA drive capability.

Key Specifications

Pinout & Package

PM6670AS is housed in a VFQFPN-24 4×4 mm exposed-pad package, optimized for thermal dissipation in high-current memory power applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power supply applications.

Compared with ISL6537IRZ and TPS51200DRCR, the PM6670AS uniquely combines COT-based VDDQ control, integrated VTT/VTTREF, and hardware-enforced S3/S5 discharge in a single VFQFPN-24 package-reducing total solution size and simplifying JEDEC compliance validation.

Availability

PM6670AS is available at Aetrix Electronics and suitable for DDR2/3 memory power supplies, digital TV systems, and SSTL/HSTL bus termination applications requiring stable component supply and long-term industrial availability.

Supply support for PM6670AS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and automotive ICs, with strong focus on industrial and consumer power solutions.

The PM6670AS belongs to ST's DDR memory power controller product line, designed specifically to simplify JEDEC-compliant DDR2/DDR3 power delivery with integrated VDDQ, VTT, and VTTREF functions in a thermally enhanced package.

FAQ

What is the purpose of the VSNS pin and how should it be routed?

The VSNS pin provides remote sensing of the VDDQ output voltage at the memory IC load point, enabling accurate regulation despite PCB trace IR drop. It must be routed as a short, low-noise, dedicated trace directly from the DDR VDDQ pin to VSNS, avoiding shared vias or noisy planes. This trace also feeds the internal VSNS/2 divider used for VTTREF and VTT scaling, making its placement critical for termination accuracy.

How does the PM6670AS achieve fast load transient response without external compensation?

The PM6670AS uses a constant-on-time (COT) control architecture with an embedded integrator that automatically compensates for DC voltage error caused by output capacitor ripple-especially critical with low-ESR ceramic capacitors. This eliminates the need for external Type-II/III compensation networks on the COMP pin, while delivering sub-10 μs transient recovery for DDR burst current steps up to 10 A.

Can the PM6670AS support both DDR2 and DDR3 on the same board?

Yes-the MODE and DDRSEL pins allow hardware-selectable configuration: tying MODE to AVCC and DDRSEL to SGND sets 1.8 V VDDQ/0.9 V VTT for DDR2; tying both to AVCC configures 1.5 V VDDQ/0.75 V VTT for DDR3. The shared VSNS/2 reference ensures consistent VTT-to-VDDQ ratio across both standards, enabling single-board dual-memory support with appropriate layout partitioning.

What happens to VTT during S3 (Suspend-to-RAM) state?

When the S3 pin is driven low, the VTT LDO enters high-impedance (Hi-Z) mode-disconnecting the VTT output from the termination bus while preserving DDR memory data in self-refresh. This reduces system standby power significantly. VTT remains Hi-Z until S3 returns high, at which point VTT resumes regulation with soft-start to prevent bus disturbance during resume.