STMicroelectronics PM6670ASTR

Overview

PM6670ASTR from STMicroelectronics is a complete DDR2/3 memory power supply controller integrating a constant-on-time (COT) buck controller for VDDQ, a 2 A sink/source LDO for VTT termination, and a ±15 mA low-noise buffered VTTREF. It delivers fixed 1.8 V (DDR2) or 1.5 V (DDR3) VDDQ outputs with ±1% accuracy, supports ceramic output capacitors, and enables S3/S4/S5 system sleep-state compliance. Used in DDR memory subsystems of digital TVs and embedded computing platforms.

For engineers reviewing the PM6670ASTR datasheet, PM6670ASTR pinout, PM6670ASTR application, or PM6670ASTR equivalent, key selection criteria include its dual-mode VDDQ output voltage selection (DDR2/DDR3), no-RSENSE current sensing via MOSFET R_DS(ON), negative current limit capability, integrated VTT/VTTREF tracking, and programmable discharge modes for JEDEC-compliant power sequencing.

Technical Context

The PM6670ASTR implements a constant-on-time (COT) control architecture for the VDDQ buck section, enabling ultra-fast load transient response without external compensation. Its embedded integrator compensates DC voltage error caused by output ripple, supporting both electrolytic and ceramic capacitors while maintaining loop stability across input voltage (4.5–36 V) and load variations.

The VTT LDO operates as a 2 A sink/source linear regulator with remote sensing (VTTSNS), foldback current limiting, and high-Z mode during S3 suspend. The VTTREF buffer delivers ±15 mA at 0.9 V (DDR2) or 0.75 V (DDR3) with ±2% accuracy relative to VSNS/2, and features dedicated discharge paths for S4/S5 tracking discharge compliance.

Key Specifications

Pinout & Package

PM6670ASTR is housed in a VFQFPN-24 4×4 mm package with exposed thermal pad, optimized for high-power density DDR memory power delivery and thermal dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power supply applications.

Compared with TPS51220RGER and ISL6537CRZ, the PM6670ASTR uniquely integrates all three functions-VDDQ buck, VTT LDO, and VTTREF buffer-in one JEDEC-compliant package, eliminating external components for DDR2/3 termination while ensuring guaranteed S3/S4/S5 sequencing behavior.

Availability

PM6670ASTR is available at Aetrix Electronics and suitable for DDR2/3 memory power supplies, digital TV systems, and SSTL/HSTL bus termination applications requiring stable component supply, long-term lifecycle support, and JEDEC-compliant power sequencing.

Supply support for PM6670ASTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with broad automotive, industrial, and consumer product portfolios.

The PM6670AS belongs to ST's DDR memory power controller product line, designed specifically to simplify JEDEC-compliant DDR2/3 power delivery with integrated VDDQ, VTT, and VTTREF functions in compact packages.

FAQ

What is the recommended output capacitor configuration for ceramic-only designs?

For ceramic-only VDDQ output, ST recommends ≥22 μF total capacitance using multiple parallel MLCCs (e.g., 4×4.7 μF X5R 1206) with ESR <5 mΩ. A 100 nF high-frequency bypass capacitor must be placed adjacent to the VSNS pin. VTT requires two 10 μF MLCCs in parallel (20 μF total) with low-ESR dielectric.

How does the PM6670ASTR achieve VTT/VTTREF tracking accuracy?

VTTREF is internally generated as VSNS/2 and buffered with ±2% accuracy. The VTT LDO regulates its output to match VTTREF using VTTSNS feedback, achieving ≤100 mV tracking error across –2 A to +2 A load steps and –40°C to +125°C ambient, per JEDEC DDR2/3 specifications.

Can the PM6670ASTR operate without an external bootstrap capacitor?

No. The BOOT pin requires a 100 nF ceramic capacitor connected between BOOT and PHASE to sustain HGATE drive during high-side conduction. Omitting this capacitor causes HGATE undervoltage, leading to shoot-through, excessive heat, and immediate device failure.

What happens to VTT during S3 (Suspend-to-RAM) state?

When S3 is pulled low, the VTT LDO enters high-impedance (Hi-Z) mode: output is disconnected from LDOIN, leakage current drops to <10 μA, and VTTSNS remains active for fast wake-up. This preserves DDR2/3 data retention while minimizing standby power.