STMicroelectronics PM6670STR
- Part No.:
- PM6670STR
- Manufacturer:
- STMicroelectronics
- Category:
- Power Management - Specialized
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
PM6670STR.pdf
- Description:
- IC CTLR DDR2/3 MEM PS 24VFQFPN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
PM6670STR from STMicroelectronics is a complete DDR2/3 memory power supply controller integrating a constant-on-time (COT) buck controller for VDDQ, a 2 A sink/source LDO for VTT, and a ±15 mA low-noise buffered VTTREF. It delivers fixed 1.8 V (DDR2) or 1.5 V (DDR3) VDDQ outputs with ±1% accuracy, supports ceramic output capacitors, and enables S3/S4/S5 sleep-state compliance. It is used in notebook computers and handheld devices requiring JEDEC-compliant DDR termination and fast transient response.
For engineers reviewing the PM6670STR datasheet, PM6670STR pinout, PM6670STR application, or PM6670STR equivalent, key selection criteria include its dual-mode VDDQ output configuration (fixed vs. adjustable), integrated VTT/VTTREF tracking architecture, no-RSENSE current sensing via MOSFET RDS(ON), negative current limit capability, and S3/S5-controlled high-Z VTT state during suspend-to-RAM.
Technical Context
The PM6670STR implements a constant-on-time (COT) PWM control loop for the VDDQ buck section, enabling ultra-fast load transient response without external compensation. Its embedded integrator compensates DC voltage error caused by output ripple, supporting both electrolytic and ceramic capacitors while maintaining stability across input voltages from 4.5 V to 28 V.
The VTT LDO operates as a 2 A sink/source linear regulator with foldback current limiting and remote sensing (VTTSNS), while the VTTREF buffer provides a ±15 mA, low-noise 0.9 V reference derived from VSNS/2. The device fully complies with JEDEC DDR2/3 termination requirements and supports system-level power states via dedicated S3 and S5 pins that control VTT high-impedance mode and coordinated discharge sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDDQ Output Voltage | Fixed 1.8 V (DDR2) or 1.5 V (DDR3); ±1% accuracy ensures SSTL18/HSTL/SSTL15 bus termination compliance. |
| VDDQ Input Range | 4.5 V to 28 V; supports wide-input industrial and notebook DC-DC front-end supplies. |
| VTT LDO Current | ±2 A sink/source; enables full DDR2/3 bidirectional termination current handling without external components. |
| VTTREF Accuracy | ±2% vs. VSNS/2; guarantees precise tracking of VDDQ/2 for accurate DDR termination reference. |
| Switching Frequency | Adjustable via VOSC pin (150–500 kHz); allows optimization of efficiency, size, and audible noise. |
| Soft-Start Time | Internally fixed at 3 ms; prevents inrush current and ensures controlled power-up of DDR memory rails. |
| Thermal Shutdown | 150 °C junction temperature; protects against thermal runaway during overload or poor PCB heatsinking. |
Pinout & Package
The PM6670STR is housed in a VFQFPN-24 4×4 mm package with exposed thermal pad, optimized for high-power density DDR memory regulation and thermal dissipation in space-constrained applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VTTGND | LDO power ground | Must connect to negative terminal of VTT output capacitor and shared low-impedance ground plane with SGND and thermal pad. |
| VTTSNS | VTT remote sense input | Enables precision regulation at DDR load point; requires short, low-noise PCB trace to memory module. |
| DDRSEL | DDR voltage mode selector | Configures VDDQ output: tied to AVCC for DDR2 (1.8 V), grounded for DDR3 (1.5 V) in fixed mode. |
| VTTREF | Buffered DDR reference output | Provides stable 0.9 V (DDR2) or 0.75 V (DDR3) reference; requires ≥22 nF ceramic bypass for stability. |
| VSNS | VDDQ remote sense input | Enables accurate VDDQ regulation at memory load; also feeds internal divider for VTTREF generation. |
| MODE | Operation mode selector | Voltage >4 V selects fixed-output mode; <4 V enables adjustable mode using external feedback resistors. |
| COMP | Error amplifier compensation node | External RC network sets loop bandwidth and phase margin for COT buck stability. |
| DSCG | Discharge mode control | Selects tracking/non-tracking discharge behavior for VDDQ, VTT, and VTTREF during power-down. |
| S3 | Suspend-to-RAM enable | Pulls VTT to high-Z state when asserted low; required for S3 power state compliance. |
| S5 | Suspend-to-disk enable | Triggers full discharge sequence for all outputs when asserted low; required for S4/S5 compliance. |
| PG | Power Good open-drain output | Asserts high when VDDQ is within ±10% of nominal; used for system power sequencing and fault detection. |
| CSNS | Current sense input | Connects to synchronous rectifier drain to set current limit threshold using MOSFET RDS(ON). |
| LGATE / HGATE | Gate driver outputs | Drive external N-channel MOSFETs; LGATE pull-down resistance ≤0.9 Ω, HGATE pull-down ≤2.7 Ω. |
| PHASE | Switch node connection | Return path for HGATE driver; must be routed with minimal inductance to reduce switching losses. |
| BOOT | Bootstrap supply input | Charges high-side gate driver bootstrap capacitor; requires 100 nF ceramic capacitor to PHASE. |
| LDOIN | VTT LDO input | Typically connected to VDDQ rail; can be supplied from lower voltage to reduce LDO power dissipation. |
| VTT | VTT LDO output | Delivers ±2 A with remote sensing; bypassed with 20 μF (2×10 μF MLCC) ceramic capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| No-RSENSE current sensing | Uses low-side MOSFET RDS(ON) instead of discrete sense resistor - reduces BOM cost and PCB area. |
| Negative current limit | Detects reverse current flow during light-load or transient conditions - prevents VDDQ rail collapse during DDR bus turnaround. |
| Ceramic capacitor support | Stable operation with MLCCs on VDDQ, VTT, and VTTREF outputs - eliminates bulk electrolytics and improves reliability. |
| Three pulse-skip modes | Selectable forced PWM, pulse-skip, and no-audible (33 kHz) pulse-skip - balances efficiency, EMI, and acoustic noise. |
| S3/S5 power management | Dedicated pins enable JEDEC-compliant suspend-to-RAM (high-Z VTT) and suspend-to-disk (coordinated discharge) behavior. |
Applications
| DDR2 Memory Power Supply | DDR3 Memory Power Supply |
|---|---|
|
Use Scenario: Providing regulated 1.8 V VDDQ and 0.9 V VTT for DDR2 SDRAM modules in ultraportable notebooks. IC Role / Device Role / Timing Role: Dual-rail controller delivering JEDEC-compliant DDR2 termination and core supply with synchronized soft-start and discharge. Use Value: Eliminates need for separate VDDQ controller and VTT LDO, reducing component count by ≥4 ICs and simplifying layout. |
Use Scenario: Generating 1.5 V VDDQ and 0.75 V VTT for DDR3 SO-DIMMs in industrial embedded systems operating from 12 V input. IC Role / Device Role / Timing Role: Integrated power management unit ensuring DDR3 bus integrity during dynamic read/write bursts and deep-sleep transitions. Use Value: Achieves <100 ns VTT transient response to ±2 A load steps - maintains signal integrity on high-speed DDR3 buses up to 1066 MT/s. |
| Notebook Computer Power Architecture | CPU Chipset I/O Supply |
|
Use Scenario: Consolidating DDR memory rail regulation in thin-and-light laptop platforms where board space and thermal headroom are constrained. IC Role / Device Role / Timing Role: Single-chip solution managing VDDQ, VTT, and VTTREF with shared thermal design and unified sequencing logic. Use Value: Reduces total solution footprint by 35% versus discrete controllers + LDOs, while enabling fanless thermal design up to 85 °C ambient. |
Use Scenario: Delivering SSTL15-compliant termination for CPU chipset I/O interfaces in server motherboard reference designs. IC Role / Device Role / Timing Role: Precision reference generator (VTTREF) and low-noise LDO (VTT) ensuring sub-25 mV VTT accuracy under ±1 A dynamic loads. Use Value: Maintains <±20 mV VTT output accuracy across -40 °C to +85 °C - meets JEDEC JESD8-12A SSTL15 specification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DDR memory power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51220RGER | Single-channel VDDQ controller only; lacks integrated VTT LDO and VTTREF buffer - requires two additional ICs for full DDR2/3 support. | Requires external 2 A VTT LDO and reference buffer; increases BOM count, layout complexity, and power sequencing overhead. | Choose when only VDDQ regulation is needed or when VTT is generated separately for thermal partitioning. |
| ISL6537CRZ | Legacy dual-rail DDR2 controller with fixed 1.8 V VDDQ and 0.9 V VTT; no DDR3 mode, no VTTREF buffer, and no S3/S5 sleep-state support. | Not compliant with DDR3 JEDEC specs or modern OS power states; limited to legacy DDR2-only designs. | Only suitable for cost-sensitive DDR2-only upgrades where S3/S5 compliance is not required. |
Compared with TPS51220RGER and ISL6537CRZ, the PM6670STR uniquely integrates full DDR2/3 dual-rail regulation, VTTREF buffering, and JEDEC-compliant S3/S5 power management in one VFQFPN-24 package - reducing system-level component count by up to 3 ICs and eliminating external sequencing logic.
Availability
PM6670STR is available at Aetrix Electronics and suitable for notebook computers, DDR2/3 memory modules, and CPU chipset I/O supplies requiring stable component supply, long-term lifecycle support, and JEDEC-compliant power sequencing.
Supply support for PM6670STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with broad manufacturing scale and automotive-grade quality systems.
The PM6670STR belongs to ST's DDR memory power controller product line, designed specifically to replace multi-IC DDR2/3 power solutions with single-chip integration targeting space-constrained, thermally sensitive computing platforms.
FAQ
What is the recommended output capacitor configuration for VDDQ when using ceramic capacitors?
Use ≥47 μF total ceramic capacitance (e.g., four 10 μF X5R 0805 MLCCs) placed close to the PM6670STR's VSNS and PGND pins. The COT control loop is optimized for ceramic output caps; no bulk electrolytic is required. Ensure low-ESR layout with short, wide traces to minimize impedance and maintain stability under fast transients.
How does the PM6670STR achieve VTT/VTTREF tracking to VDDQ/2?
The PM6670STR internally divides the VSNS voltage by two and uses it as the reference for both VTTREF buffer and VTT LDO error amplifiers. VTTSNS and VSNS must be routed as matched-length, low-noise differential pairs to preserve tracking accuracy. This architecture ensures VTT remains within ±20 mV of VDDQ/2 across load and temperature - meeting JEDEC DDR2/3 termination tolerance.
Can the PM6670STR operate in DDR2 and DDR3 modes simultaneously?
No. DDRSEL pin configures the device for either DDR2 (1.8 V VDDQ / 0.9 V VTT) or DDR3 (1.5 V VDDQ / 0.75 V VTT) operation - it cannot generate both voltages concurrently. The MODE pin further selects fixed-output or adjustable mode, but the DDRSEL setting determines the JEDEC standard compliance target and internal reference scaling.
What happens to VTT during S3 (suspend-to-RAM) state?
When the S3 pin is driven low, the VTT LDO enters high-impedance state - disconnecting the output from LDOIN and preventing current flow into or out of the DDR bus. This preserves memory contents during suspend while eliminating VTT-related standby power loss. VTT resumes regulation immediately upon S3 deassertion, with no re-start delay.
PM6670STR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Memory, DDR2/DDR3 Regulator
- Current - Supply:
- 800µA
- Voltage - Supply:
- 4.5V ~ 28V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-VFQFPN (4x4)
PM6670STR FAQ
1.How can I place an order for PM6670STR through Aetrix?
Please submit a Request for Quotation (RFQ) for PM6670STR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM6670STR reliable?
The price and inventory of PM6670STR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM6670STR is usually 5 days.
3.What payment methods are accepted for PM6670STR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM6670STR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM6670STR?
PM6670STR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM6670STR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM6670STR?
For technical support, including PM6670STR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM6670STR requirements.
6.How does Aetrix verify that PM6670STR is sourced from the original manufacturer or authorized distributors?
All PM6670STR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM6670STR meets industry standards.
7.What is the process for return or replacement of PM6670STR?
All PM6670STR units undergo pre-shipment inspection (PSI). If there is an issue with PM6670STR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM6670STR part is unused and in its original packaging.
Return procedure for PM6670STR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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