Nexperia USA Inc. PMC85XP,115

Overview

PMC85XP,115 from Nexperia is a dual-function discrete component integrating a 30 V P-channel Trench MOSFET and a pre-biased NPN Resistor-Equipped Transistor (RET) in a single DFN2020-6 (SOT1118) package. It delivers R_DS(on) = 85 mΩ @ V_GS = −4.5 V, I_D = −2.6 A, and includes built-in bias resistors (R1 = 4.7 kΩ, R2 = 47 kΩ) for direct logic-level drive - used as a high-side load switch and USB overvoltage protection element in portable power management circuits.

For engineers reviewing the PMC85XP,115 datasheet, PMC85XP,115 pinout, PMC85XP,115 application, or PMC85XP,115 equivalent, this device serves as an integrated high-side switching solution with thermal-enhanced drain pad, requiring no external base resistors and supporting compact battery-powered designs where space, thermal performance, and simplified drive are critical.

Technical Context

The PMC85XP,115 combines two independent semiconductor functions on one die: a P-channel enhancement-mode MOSFET with trench technology and a monolithic NPN RET featuring integrated R1 (4.7 kΩ) and R2 (47 kΩ) biasing resistors. Its gate threshold voltage (V_GS(th)) ranges from −0.45 V to −1.0 V, enabling reliable turn-on from 3.3 V logic, while the NPN section provides 100 mA output current with V_CE(sat) ≤ 100 mV at I_C = 5 mA.

Thermal design is supported by an exposed drain pad delivering R_th(j-sp) = 10–15 K/W and R_th(j-a) = 93–107 K/W (with 6 cm² drain pad), and the device operates across −55 °C to +150 °C junction temperature. The dual topology allows coordinated control of power path (MOSFET) and enable/sense logic (RET) without interposer routing or discrete bias networks.

Key Specifications

Pinout & Package

DFN2020-6 (SOT1118) is a leadless, thermally enhanced surface-mount package with an exposed drain pad on the bottom side for optimal heat transfer. Dimensions: 2.0 mm × 2.0 mm × 0.65 mm max height; six terminals arranged in a single row with pin 1 at top-left in top-view orientation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-function high-side switching applications.

Compared with PMZB200UN,115 and BC847B,215, the PMC85XP,115 uniquely integrates both power switching and logic interface in one thermally optimized package - reducing component count, improving timing coordination between enable and power stages, and minimizing parasitic inductance in portable power paths.

Availability

PMC85XP,115 is available at Aetrix Electronics and suitable for portable device charging switches, USB overvoltage protection circuits, and high-side load switching applications requiring stable component supply, consistent parametric performance, and long-term lifecycle continuity.

Supply support for PMC85XP,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified and industrial-grade components.

The PMC85XP,115 belongs to Nexperia's "Load Switch & Power Management" product line, designed specifically for space-constrained, battery-powered applications demanding integrated power control and intelligent enable logic in minimal footprint.

FAQ

What is the maximum continuous drain current for the PMC85XP,115 at 100 °C ambient?

The maximum continuous drain current is −1.6 A at T_amb = 100 °C with V_GS = −4.5 V, per Absolute Maximum Ratings Table 5. This derating reflects thermal limits of the DFN2020-6 package on standard FR4 PCBs without extended copper pour. For higher current, thermal pad soldering and ≥6 cm² copper area are required to maintain junction temperature below 150 °C.

Can the NPN RET section drive a 10 kΩ pull-up load directly?

Yes - the NPN RET delivers 100 mA output current and exhibits V_CE(sat) ≤ 100 mV at I_C = 5 mA, meaning it can fully saturate against a 10 kΩ pull-up to 5 V (I_C = 0.5 mA). At that load, collector voltage remains below 100 mV, ensuring clean logic-low assertion for microcontroller interrupt or enable inputs.

Is the exposed drain pad electrically connected to any internal node?

Yes - the exposed drain pad is electrically and thermally connected to Pin 3 (D) and Pin 8 (D) as shown in the simplified outline graphic. It must be soldered to a PCB copper pour tied to the drain net; floating or grounded connection will cause functional failure or thermal overstress.

Does the PMC85XP,115 support 1.8 V logic-level gate drive?

No - the gate threshold voltage minimum is −0.45 V, but reliable enhancement requires V_GS ≤ −1.2 V for sufficient channel inversion. At 1.8 V logic, V_GS = −1.8 V is achievable only if source is at 1.8 V and gate is at 0 V; however, R_DS(on) rises sharply below −2.5 V, reaching 140 mΩ typ at V_GS = −2.5 V. Use −3.3 V or −4.5 V drive for optimal performance.