Nexperia USA Inc. PMP3906AYSH

Overview

PMP3906AYS from Nexperia is a matched PNP/PNP double transistor in SOT363-3 (TSSOP6) package, designed for precision analog functions requiring tight parameter matching. It delivers ±2 mV base-emitter voltage matching and 0.95–1.00 DC current gain ratio (hFE1/hFE2) at −2 mA collector current, with −40 V VCEO and −200 mA IC per transistor, commonly used in high-fidelity current mirror circuits.

For engineers reviewing the PMP3906AYS datasheet, PMP3906AYS pinout, PMP3906AYS application, or PMP3906AYS equivalent, key selection criteria include matched hFE tracking across temperature, low VBE mismatch under bias, application-optimized pinout for differential layout, and thermal derating on FR4 PCBs.

Technical Context

This dual PNP transistor pair integrates two electrically matched transistors on a single die within a 6-pin TSSOP package. Matching is specified at VCE = −5 V, IC = −2 mA, Tamb = 25 °C for VBE and at VCE = −1 V, IC = −10 mA for hFE ratio - both critical for stable biasing in symmetrical analog topologies.

The device operates with open-base VCEO = −40 V and VEBO = −6 V, supports pulsed IC up to −200 mA, and exhibits fT = 250 MHz at VCE = −20 V, IC = −10 mA. Its transient thermal impedance (Zth(j-a)) and power derating curve are defined for standard FR4 PCB mounting with tin-plated copper.

Key Specifications

Pinout & Package

Package: SOT363-3 (TSSOP6), 2.2 mm × 1.35 mm × 0.95 mm body, 0.65 mm lead pitch, plastic surface-mount package with exposed pad not present.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar matched PNP pair applications.

Compared with BC847BPDW1T3G and MBT3906DW1T1G, PMP3906AYS uniquely guarantees both hFE ratio ≥0.95 and VBE mismatch ≤2 mV - essential for sub-0.1% error in current mirrors and differential pairs where untrimmed matching is required.

Availability

PMP3906AYS is available at Aetrix Electronics and suitable for current mirror circuits, differential amplifiers, active load implementations, and temperature-stable reference designs requiring stable component supply and verified matching performance.

Supply support for PMP3906AYS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices with focus on efficiency, reliability, and miniaturization.

PMP3906AYS belongs to Nexperia's matched bipolar transistor product line, engineered specifically for precision analog signal conditioning and biasing applications where parameter tracking across temperature and unit-to-unit is critical.

FAQ

What is the maximum continuous collector current per transistor in PMP3906AYS?

The absolute maximum continuous collector current per transistor is −200 mA, as defined in the limiting values table under I_C. This rating applies at T_amb ≤ 25 °C with proper PCB thermal relief; derating is required above 25 °C using the published 357 K/W R_th(j-a) curve.

How is hFE matching defined for PMP3906AYS, and under what conditions is it guaranteed?

hFE matching is defined as hFE1/hFE2, where the smaller hFE value is divided by the larger, guaranteeing a minimum ratio of 0.95. This is tested at V_CE = −1 V, I_C = −10 mA, and T_amb = 25 °C per transistor, ensuring predictable current division in mirror configurations without external trimming.

Can PMP3906AYS be used in automotive applications?

No - PMP3906AYS is not automotive-qualified. The datasheet explicitly states it is "non-automotive qualified" and lacks AEC-Q101 stress testing, extended temperature validation beyond −55 °C to +150 °C operational limits, or PPAP documentation. Use only in industrial, consumer, or communications equipment.

What is the recommended soldering profile for the SOT363-3 package?

The manufacturer specifies reflow soldering using the footprint in Figure 11: 2.65 mm × 2.35 mm pad layout with 0.5 mm × 0.5 mm pads for pins 1–6 and 0.6 mm × 0.6 mm for outer pins. Peak reflow temperature must not exceed 260 °C for ≤30 seconds, per JEDEC J-STD-020 moisture sensitivity level 1 requirements.