Nexperia USA Inc. PMP5201Y,115
- Part No.:
- PMP5201Y,115
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
PMP5201Y,115.pdf
- Description:
- TRANS 2PNP 45V 100MA 6-TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,902
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Product details
Overview
PMP5201Y from Nexperia is a PNP/PNP matched double transistor in SOT363-3 (TSSOP6) package, designed for precision analog functions requiring tight hFE matching (0.98–1.02) and VBE matching (±2 mV) at −5 V VCE and −2 mA IC. It supports 45 V VCEO, 100 mA IC per transistor, and operates across −65 °C to 150 °C ambient. Used in current mirror and differential amplifier circuits where transistor pair symmetry is critical.
For engineers reviewing the PMP5201Y datasheet, PMP5201Y pinout, PMP5201Y application, or PMP5201Y equivalent, key selection criteria include matched DC current gain, base-emitter voltage tracking, thermal resistance (416 K/W per device), SOT363-3 footprint compatibility, and PNP-only dual-transistor topology for high-side current sensing and balanced signal conditioning.
Technical Context
This matched double transistor integrates two identical PNP silicon epitaxial planar transistors on a single die with monolithic matching-ensuring consistent hFE (200–450 typ.) and VBE (−650 mV typ. at −2 mA) across temperature. Its complementary NPN/NPN counterpart is PMP4201Y; PNP/NPN complement is not offered.
The device uses an application-optimized pinout (B1, B2, C2, E2, E1, C1) enabling direct current mirror wiring without external crossover traces. Thermal design leverages 300 mW total power dissipation (per device) on FR4 PCB with single-sided copper, supported by Rth(j-a) = 416 K/W.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −45 V per transistor: maximum safe collector-emitter voltage with open base, defining high-side bias headroom in current mirrors. |
| IC | −100 mA per transistor: continuous collector current rating, supporting precision mirroring up to 100 mA output. |
| hFE1/hFE2 | 0.98–1.02: guaranteed current gain matching ratio, enabling <2% error in mirrored current transfer. |
| VBE1−VBE2 | ±2 mV at −2 mA IC: base-emitter voltage mismatch, critical for common-mode rejection in differential pairs. |
| fT | 100–175 MHz typical: transition frequency at −10 mA IC, supporting audio and low-MHz signal amplification. |
| Rth(j-a) | 416 K/W per device: junction-to-ambient thermal resistance on standard FR4 PCB, guiding heatsinking requirements. |
| Ptot | 300 mW per device: total power dissipation limit at Tamb ≤ 25 °C, constraining simultaneous conduction in both transistors. |
Pinout & Package
SOT363-3 (TSSOP6) plastic surface-mounted package: 2.2 mm × 1.35 mm body, 0.65 mm pitch, 6-lead, transparent top view with pin 1 index. Designed for reflow soldering with defined footprint (2.35 mm × 2.65 mm solder lands).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base TR1 | Controls first PNP transistor; referenced to E1 for local current gain setting in mirror or diff-amp configurations. |
| 2 | Base TR2 | Controls second PNP transistor; paired with B1 to enable matched biasing in differential or mirror topologies. |
| 3 | Collector TR2 | Output node of TR2; connected to load or next stage in current mirror (Fig. 9) or differential output (Fig. 10). |
| 4 | Emiter TR2 | Emitter reference for TR2; tied to common emitter node in differential pair or grounded in basic current mirror. |
| 5 | Emiter TR1 | Emitter reference for TR1; forms shared emitter node with E2 in differential configuration or connects to supply in high-side mirror. |
| 6 | Collector TR1 | Input/reference node of TR1; receives input current in mirror or drives base of next stage in active load applications. |
Key Features
| Feature | Design Value |
|---|---|
| Monolithic hFE matching | 0.98–1.02 ratio ensures <2% current error between transistors under matched bias conditions. |
| VBE tracking | ±2 mV mismatch enables >60 dB common-mode rejection in differential amplifiers at 25 °C. |
| Application-optimized pinout | B1/B2 adjacent, C1/E1/C2/E2 arranged to minimize trace crossovers in current mirror PCB layout (Fig. 9). |
| Thermal performance | 416 K/W Rth(j-a) per device allows 300 mW dissipation on standard FR4, supporting stable operation at full rated current. |
| High-voltage PNP structure | −45 V VCEO supports operation in 24 V and 36 V industrial supply rails with margin for transients. |
Applications
| Current Mirror | Differential Amplifier |
|---|---|
|
Use Scenario: Precision current replication in sensor biasing, LED drivers, or analog front-end references. IC Role / Device Role / Timing Role: Dual PNP transistors act as matched current source/sink pair, with TR1 as reference and TR2 as output leg. Use Value: ±2 mV VBE mismatch and 0.98–1.02 hFE ratio ensure <2.5% current error over −55 °C to 100 °C operating range. |
Use Scenario: Input stage of operational amplifiers or instrumentation amplifiers requiring high CMRR. IC Role / Device Role / Timing Role: TR1 and TR2 form the matched input pair; B1/B2 receive differential inputs, E1/E2 share common emitter node. Use Value: Tight VBE and hFE matching directly improves DC CMRR by >15 dB versus discrete transistor solutions. |
| Active Load Circuit | High-Side Current Sensing |
|
Use Scenario: Constant-current active load in voltage-controlled oscillator (VCO) or filter tuning circuits. IC Role / Device Role / Timing Role: TR1 configured as diode-connected PNP (C1→B1), TR2 as controlled current sink (B2 biased externally). Use Value: Monolithic matching eliminates thermal drift between diode and transistor, stabilizing load current vs. temperature. |
Use Scenario: High-side current monitoring in 24 V industrial power supplies or motor control feedback loops. IC Role / Device Role / Timing Role: TR1 acts as current-sense transistor with emitter tied to supply; TR2 mirrors sensed current to ground-referenced shunt. Use Value: −45 V VCEO rating enables direct connection to 24 V rail; matched hFE ensures accurate scaling of sense current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar matched PNP transistor pair applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PMP4201Y | NPN/NPN matched pair; same SOT363-3 package, identical hFE/VBE matching specs, but opposite polarity. | Required for low-side current mirrors or NPN-input differential stages; not interchangeable in high-side or PNP-biased circuits. | Select when circuit topology requires NPN devices-e.g., emitter-follower outputs or ground-referenced inputs. |
| BCM847DS | PNP/NPN matched pair in SOT363; hFE matching ±5%, no VBE matching spec; lower VCEO (−45 V same), higher fT (250 MHz). | Supports complementary switching but lacks precision analog matching; unsuitable for current mirrors demanding <2% error. | Choose only for digital switching or mixed-polarity bias networks-not for precision analog matching tasks. |
Compared with PMP4201Y, PMP5201Y enables high-side current sourcing and PNP-input stages; versus BCM847DS, it delivers verified ±2 mV VBE matching essential for >60 dB CMRR, not just switching functionality.
Availability
PMP5201Y is available at Aetrix Electronics and suitable for current mirror circuits, differential amplifiers, active load designs, and high-side current sensing applications requiring stable component supply and matched transistor performance.
Supply support for PMP5201Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable discrete, logic, and MOSFET devices with focus on efficiency, reliability, and miniaturization.
PMP5201Y belongs to Nexperia's matched transistor family, engineered specifically for precision analog functions where monolithic pairing eliminates inter-die thermal and process variation in current mirrors and differential pairs.
FAQ
What is the maximum continuous collector current per transistor in the PMP5201Y?
The PMP5201Y supports −100 mA continuous collector current per transistor under normal operating conditions (Tamb ≤ 25 °C, FR4 PCB). At higher ambient temperatures or with reduced airflow, derating applies per the thermal resistance of 416 K/W per device and 300 mW total power limit.
Can PMP5201Y be used as a drop-in replacement for discrete PNP transistors in existing current mirror designs?
Yes-if the PCB layout accommodates the SOT363-3 (TSSOP6) footprint and pinout (B1, B2, C2, E2, E1, C1). Its monolithic matching provides superior hFE and VBE tracking versus discrete solutions, improving accuracy and thermal stability without circuit redesign.
Does PMP5201Y have automotive qualification?
No. The PMP5201Y is not automotive-qualified. It is specified for industrial and general-purpose applications across −65 °C to 150 °C ambient, but has not undergone AEC-Q101 stress testing or been validated for automotive safety-critical systems.
How does the hFE matching tolerance affect current mirror accuracy?
With hFE1/hFE2 guaranteed between 0.98 and 1.02, the current mirror output error is bounded to ±2% under matched bias conditions. This exceeds typical discrete transistor matching (±10–20%) and enables stable biasing in precision op-amp input stages and sensor interfaces.
PMP5201Y,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Transistor Type:
- 2 PNP (Dual) Matched Pair
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 45V
- Vce Saturation (Max) @ Ib, Ic:
- 400mV @ 5mA, 100mA
- Current - Collector Cutoff (Max):
- 15nA (ICBO)
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 200 @ 2mA, 5V
- Power - Max:
- 300mW
- Frequency - Transition:
- 175MHz
- Operating Temperature:
- 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-TSSOP
PMP5201Y,115 FAQ
1.How can I place an order for PMP5201Y,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for PMP5201Y,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PMP5201Y,115 reliable?
The price and inventory of PMP5201Y,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMP5201Y,115 is usually 5 days.
3.What payment methods are accepted for PMP5201Y,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMP5201Y,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PMP5201Y,115?
PMP5201Y,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PMP5201Y,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PMP5201Y,115?
For technical support, including PMP5201Y,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMP5201Y,115 requirements.
6.How does Aetrix verify that PMP5201Y,115 is sourced from the original manufacturer or authorized distributors?
All PMP5201Y,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMP5201Y,115 meets industry standards.
7.What is the process for return or replacement of PMP5201Y,115?
All PMP5201Y,115 units undergo pre-shipment inspection (PSI). If there is an issue with PMP5201Y,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PMP5201Y,115 part is unused and in its original packaging.
Return procedure for PMP5201Y,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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