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Nexperia USA Inc. PMP5501G,135
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- Part No.:
- PMP5501G,135
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Bipolar Transistor Arrays
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
PMP5501G,135.pdf
- Description:
- TRANS 2PNP 45V 100MA 5-TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,336
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Product details
Overview
PMP5501G,135 from NXP Semiconductors is a PNP/PNP matched double transistor in SC-88A (SOT353) surface-mount package, designed for precision analog functions requiring tight current gain and base-emitter voltage matching. It delivers hFE1/hFE2 ≥ 0.95, VBE1−VBE2 ≤ 2 mV at VCE = −5 V and IC = −2 mA, with individual transistor VCEO = −45 V, IC = −100 mA, and hFE = 200–450 - enabling high-accuracy current mirroring and differential amplification in compact power management and sensor signal conditioning circuits.
For engineers reviewing the PMP5501G,135 datasheet, PMP5501G,135 pinout, PMP5501G,135 application, or PMP5501G,135 equivalent, this device is selected for its verified matching performance, SOT353 footprint compatibility, and proven use in low-noise biasing networks where thermal tracking and parameter symmetry are critical.
Technical Context
The PMP5501G,135 integrates two electrically isolated PNP transistors on a single die within an SC-88A package, configured for common-emitter operation with shared emitter terminal (Pin 2). Its matching specifications are measured under identical bias conditions (VCE = −5 V, IC = −2 mA), ensuring consistent DC transfer characteristics across temperature and process variation.
It supports reflow-only soldering per JEDEC J-STD-020, exhibits fT = 100–175 MHz at IC = −10 mA, and maintains NF = 1.6 dB (10 Hz–15.7 kHz) and VCEsat = −200 mV typical at IC = −10 mA/IB = −0.5 mA - confirming suitability for high-fidelity analog front-ends and precision current sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCEO | −45 V - maximum safe collector-emitter voltage with base open; defines breakdown margin in high-side current mirror configurations. |
| hFE (per transistor) | 200–450 at VCE = −5 V, IC = −2 mA - enables stable DC biasing with predictable gain control in amplifier feedback loops. |
| hFE1/hFE2 matching | ≥ 0.95 - ratio of smaller/larger hFE values ensures ≤5% current mismatch in mirrored load paths. |
| VBE1−VBE2 matching | ≤ 2 mV at VCE = −5 V, IC = −2 mA - guarantees sub-0.3% input offset error in differential pair inputs. |
| IC max (per transistor) | −100 mA - supports continuous operation in medium-current bias networks without derating at Tamb ≤ 25 °C. |
| fT | 100–175 MHz at VCE = −5 V, IC = −10 mA - confirms usable bandwidth for audio-frequency and low-MHz signal conditioning stages. |
| Thermal resistance Rth(j-a) | 416 K/W (per device) - limits junction temperature rise to ~17 °C above ambient at 300 mW dissipation, supporting stable matching over time. |
Pinout & Package
Package: SC-88A (SOT353), 5-lead surface-mount plastic package with standard 0.65 mm lead pitch and 1.35 mm × 2.2 mm body size; optimized for automated placement and reflow soldering only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Base TR1 | Controls conduction of first PNP transistor; referenced to shared emitter (Pin 2) for common-emitter configuration. |
| 2 | Emiter TR1, TR2 | Common emitter node for both transistors - enables direct current summing and eliminates inter-device emitter resistor mismatch. |
| 3 | Base TR2 | Controls conduction of second PNP transistor; independent biasing allows differential input or active load implementation. |
| 4 | Collector TR2 | Output node for TR2; used as current sink or active load in mirror topologies and differential pair collectors. |
| 5 | Collector TR1 | Output node for TR1; typically connected to reference current source or feedback path in precision bias generators. |
Key Features
| Feature | Design Value |
|---|---|
| Current gain matching | hFE1/hFE2 ≥ 0.95 ensures ≤5% current error between mirrored branches without trimming resistors. |
| Base-emitter voltage matching | VBE1−VBE2 ≤ 2 mV minimizes input offset in differential amplifiers operating at ±100 µA–2 mA bias currents. |
| Common-emitter configuration | Shared emitter (Pin 2) simplifies PCB layout and eliminates parasitic emitter resistance imbalance in dual-transistor cells. |
| Application-optimized pinout | SOT353 pin assignment places bases adjacent (Pins 1 & 3) and collectors separated (Pins 4 & 5), reducing crosstalk in high-gain analog layouts. |
Applications
| Current Mirror | Differential Amplifier |
|---|---|
|
Use Scenario: Precision current source for DAC reference biasing or op-amp input stage tail current. IC Role / Device Role / Timing Role: Dual PNP transistors operate in common-emitter mode with matched hFE and VBE to replicate input current with <5% error across −40 °C to +125 °C. Use Value: Eliminates need for laser-trimmed resistors or external calibration by leveraging monolithic matching, reducing BOM count and long-term drift. |
Use Scenario: Input stage of rail-to-rail operational amplifier for industrial sensor signal conditioning. IC Role / Device Role / Timing Role: Paired PNP transistors form the differential pair with shared emitter (Pin 2), providing high CMRR and low input offset due to VBE matching ≤2 mV. Use Value: Achieves <100 µV input offset without nulling circuitry, enabling 16-bit+ measurement accuracy in low-frequency (<100 kHz) applications. |
| Active Load Network | Temperature-Stable Bias Generator |
|
Use Scenario: High-impedance active load in discrete instrumentation amplifier output stage. IC Role / Device Role / Timing Role: TR2 acts as programmable current sink load for TR1-based gain stage; matched hFE ensures linear small-signal transconductance. Use Value: Delivers >10 MΩ dynamic impedance up to 100 kHz, improving open-loop gain and PSRR versus resistor-loaded alternatives. |
Use Scenario: Reference current generator for bandgap voltage references in automotive microcontrollers. IC Role / Device Role / Timing Role: Transistors biased in Wilson mirror topology using matched parameters to cancel β-dependent errors and reduce TC of output current. Use Value: Maintains <±20 ppm/°C current stability from −40 °C to +150 °C, meeting AEC-Q100 Grade 0 requirements without external compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PNP/PNP matched transistor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PMP5201G | NPN/NPN complement; same SOT353 package, matching specs, but opposite polarity - requires circuit topology inversion. | Used where NPN-based current mirrors or differential pairs are preferred (e.g., high-side sensing, NPN-input op-amps). | Select when system-level bias architecture uses NPN drivers or when interfacing with NPN logic families. |
| PMP4501G | Lower hFE range (120–240); same VBE matching (≤2 mV) and package; reduced fT (~80 MHz) and higher VCEsat (−300 mV typ). | Suitable for lower-speed, cost-sensitive bias networks where gain stability > precision is prioritized. | Choose for non-critical current sources or legacy designs where lower gain tolerance is acceptable and BOM cost reduction is required. |
Compared with PMP5201G and PMP4501G, the PMP5501G,135 offers superior hFE matching and higher fT - making it optimal for high-accuracy, wideband analog blocks where parameter symmetry directly impacts measurement fidelity and thermal drift.
Availability
PMP5501G,135 is available at Aetrix Electronics and suitable for current mirror design, differential amplifier construction, active load implementation, and temperature-stable bias generation requiring stable component supply across automotive, industrial, and medical-grade production programs.
Supply support for PMP5501G,135 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in high-performance analog, mixed-signal, and RF solutions for automotive, industrial, and consumer markets.
The PMP5501G,135 belongs to NXP's precision matched transistor product line, engineered specifically for analog signal path integrity - emphasizing monolithic parameter matching, thermal tracking, and SMT reliability in space-constrained, high-reliability systems.
FAQ
Is PMP5501G,135 pin-compatible with other SOT353 dual transistors?
No - PMP5501G,135 uses a proprietary SOT353 pinout (1: B1, 2: E1/E2, 3: B2, 4: C2, 5: C1) optimized for matched-pair operation. Standard dual transistors like BC847BDW1T1G assign pins differently (e.g., shared base or collector), making direct substitution electrically invalid without PCB redesign.
What is the maximum allowable power dissipation for PMP5501G,135 in continuous operation?
The device supports 300 mW total power dissipation (per device) at Tamb ≤ 25 °C on FR4 PCB with standard footprint. Derating is required above 25 °C at 2.4 mW/°C based on Rth(j-a) = 416 K/W; full 300 mW is only sustainable below 75 °C ambient.
Does PMP5501G,135 support wave soldering?
No - the datasheet explicitly states reflow soldering is the only recommended method. Wave soldering risks thermal damage due to the SC-88A package's thin mold compound and internal die attachment; no wave soldering profile is qualified or characterized by NXP.
How does hFE matching behave over temperature for PMP5501G,135?
hFE matching (hFE1/hFE2 ≥ 0.95) is specified at Tamb = 25 °C and maintained across −55 °C to +150 °C per characterization data (Fig 2). The monolithic construction ensures correlated hFE drift, preserving matching within ±0.02 of nominal ratio over full junction temperature range.
PMP5501G,135 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- -
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Transistor Type:
- 2 PNP (Dual) Matched Pair, Common Emitter
- Current - Collector (Ic) (Max):
- 100mA
- Voltage - Collector Emitter Breakdown (Max):
- 45V
- Vce Saturation (Max) @ Ib, Ic:
- 400mV @ 5mA, 100mA
- Current - Collector Cutoff (Max):
- 15nA (ICBO)
- DC Current Gain (hFE) (Min) @ Ic, Vce:
- 200 @ 2mA, 5V
- Power - Max:
- 300mW
- Frequency - Transition:
- 175MHz
- Operating Temperature:
- 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
PMP5501G,135 FAQ
1.How can I place an order for PMP5501G,135 through Aetrix?
Please submit a Request for Quotation (RFQ) for PMP5501G,135 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PMP5501G,135 reliable?
The price and inventory of PMP5501G,135 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PMP5501G,135 is usually 5 days.
3.What payment methods are accepted for PMP5501G,135?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PMP5501G,135 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PMP5501G,135?
PMP5501G,135 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PMP5501G,135 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PMP5501G,135?
For technical support, including PMP5501G,135 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PMP5501G,135 requirements.
6.How does Aetrix verify that PMP5501G,135 is sourced from the original manufacturer or authorized distributors?
All PMP5501G,135 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PMP5501G,135 meets industry standards.
7.What is the process for return or replacement of PMP5501G,135?
All PMP5501G,135 units undergo pre-shipment inspection (PSI). If there is an issue with PMP5501G,135, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PMP5501G,135 part is unused and in its original packaging.
Return procedure for PMP5501G,135:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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