Nexperia USA Inc. PMP5501V,115

Overview

PMP5501V from Nexperia is a PNP/PNP matched double transistor in SOT666 package, designed for precision analog functions requiring tight current gain (hFE1/hFE2 ≥ 0.95) and base-emitter voltage matching (≤ 2 mV) at −5 V VCE and −2 mA IC. It supports −45 V VCEO, −100 mA IC per transistor, and operates across −65 °C to +150 °C ambient. Used in high-accuracy current mirrors and differential amplifiers where transistor pair matching directly determines circuit linearity and offset.

For engineers reviewing the PMP5501V datasheet, PMP5501V pinout, PMP5501V application, or PMP5501V equivalent, this page delivers verified pin functions, real-world matching specs, thermal resistance (416 K/W device-level), and application-specific design meaning - not generic transistor descriptions.

Technical Context

The PMP5501V integrates two fully isolated PNP transistors on a single die within an ultra-small SOT666 package, enabling matched performance without external layout dependency. Its hFE matching (0.95–1.0) and VBE matching (≤ 2 mV) are specified under identical bias (VCE = −5 V, IC = −2 mA, Tamb = 25 °C), ensuring predictable behavior in feedback and differential topologies.

Thermal design is constrained by device-level Rth(j-a) = 416 K/W (FR4 PCB, reflow soldered), and absolute maximum ratings include −45 V VCEO, −100 mA IC per transistor, and 300 mW total device power dissipation. The matched pair shares no internal connection - pins 1–6 provide independent access to B1, B2, C2, E2, E1, C1.

Key Specifications

Pinout & Package

SOT666 plastic surface-mount package: 6-pin, 0.5 mm pitch, 1.6 mm × 1.2 mm × 0.55 mm body, reflow-solder only. Fully isolated dual-transistor structure with no internal interconnection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar matched PNP transistor pair applications.

Compared with PMP5201V (NPN/NPN) and PMP4501V (NPN/PNP), the PMP5501V is the sole option delivering verified PNP/PNP matching - essential for low-offset PNP-biased analog building blocks where polarity and pairing fidelity cannot be compromised.

Availability

PMP5501V is available at Aetrix Electronics and suitable for precision analog design, current mirror implementation, and differential amplifier construction requiring stable component supply and guaranteed transistor matching across production lots.

Supply support for PMP5501V includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with manufacturing rooted in process control and automotive-grade quality systems.

The PMP5501V belongs to Nexperia's matched bipolar transistor family, engineered specifically for analog signal conditioning where parametric consistency between paired devices is non-negotiable - not general-purpose switching.

FAQ

What is the maximum allowable power dissipation for the PMP5501V device?

The PMP5501V has a total device power dissipation limit of 300 mW at Tamb ≤ 25 °C on an FR4 PCB with single-sided copper and standard footprint. This value decreases linearly with rising ambient temperature, reaching zero at Tj = 150 °C. Derating must follow the 416 K/W Rth(j-a) curve, and reflow soldering is the only approved assembly method.

Can the PMP5501V be used in automotive applications?

No. The PMP5501V is explicitly marked as non-automotive qualified in its revision history and legal disclaimers. It has not undergone AEC-Q101 stress testing or automotive qualification processes. For automotive use, engineers must select Nexperia's designated automotive-grade variants, which carry separate part numbers and qualification documentation.

How is the hFE matching specification tested and guaranteed?

Nexperia measures hFE1/hFE2 on every production lot using automated test equipment at VCE = −5 V, IC = −2 mA, and Tamb = 25 °C. The 0.95 minimum ratio is a parametric screen applied during final test; units failing this criterion are rejected. Matching is guaranteed per device, not per wafer or batch average.

Is there a recommended PCB layout for minimizing thermal coupling between the two transistors?

Although the transistors are internally isolated, thermal coupling affects matching drift. Nexperia recommends symmetric copper pour around both devices, equal trace lengths to bases/emitters, and avoidance of large thermal masses adjacent to one transistor. The SOT666 footprint in Figure 12 (2.75 × 2.45 mm solder lands) is optimized for balanced heat spreading across the dual-die structure.