Nexperia USA Inc. PMP5501Y,115

Overview

PMP5501Y from Nexperia is a PNP/PNP matched double transistor in SOT363-3 (TSSOP6) package, designed for precision analog functions requiring tight hFE and VBE matching between two integrated PNP transistors. It delivers ±2 mV base-emitter voltage matching and 0.95–1.00 hFE ratio at IC = −2 mA, with −45 V VCEO and −100 mA IC rating per transistor - enabling stable current mirroring and differential amplification in automotive-grade signal conditioning circuits.

For engineers reviewing the PMP5501Y datasheet, PMP5501Y pinout, PMP5501Y application, or PMP5501Y equivalent, this device supports AEC-Q101-compliant designs where transistor pair matching, thermal tracking, and low-noise biasing are critical - especially in high-reliability current mirrors and differential input stages operating across −55 °C to +150 °C ambient.

Technical Context

This dual PNP transistor integrates two electrically isolated but thermally coupled transistors on a single die within a 6-pin TSSOP package. Its matched characteristics stem from monolithic fabrication: hFE1/hFE2 ratio of 0.95–1.00 and VBE1−VBE2 ≤ ±2 mV under identical bias (VCE = −5 V, IC = −2 mA, Tamb = 25 °C), ensuring minimal offset drift over temperature.

The device operates as a discrete pair - not a composite or Darlington - with independent base, emitter, and collector terminals for each transistor. Its 175 MHz fT, 3.1 dB noise figure at 1 kHz, and 200 mW per-device power dissipation support high-fidelity analog front-end roles in sensor interfaces and feedback control loops.

Key Specifications

Pinout & Package

SOT363-3 (TSSOP6) plastic surface-mount package: 2.2 mm × 1.35 mm footprint, 0.65 mm pitch, 0.95 mm max height; optimized for reflow soldering only.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar matched PNP transistor pair applications.

Compared with PMP5201Y and PMP4501Y, the PMP5501Y uniquely delivers matched PNP behavior essential for negative-supply current mirrors and low-offset PNP differential inputs - neither alternative replicates its monolithic PNP pair symmetry or VBE tracking performance.

Availability

PMP5501Y is available at Aetrix Electronics and suitable for automotive sensor interfaces, industrial current sensing, precision current mirrors, and differential amplifier designs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PMP5501Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability discrete and logic devices, with leadership in automotive-qualified components and advanced packaging.

The PMP5501Y belongs to Nexperia's matched transistor family, engineered specifically for analog signal integrity in automotive and industrial systems where thermal tracking and parametric matching are non-negotiable.

FAQ

Is PMP5501Y pin-compatible with older PMP5501V or PMP5501G variants?

Yes - PMP5501Y uses the same SOT363-3 (TSSOP6) package and identical pinout as prior revisions. The 2026 datasheet confirms no mechanical or electrical changes to pin assignment, though marking code and internal process have been updated for improved matching yield and AEC-Q101 compliance.

What is the maximum continuous collector current per transistor at 100 °C ambient?

At Tamb = 100 °C, the maximum continuous IC is derated to −60 mA per transistor, based on Rth(j-a) = 625 K/W and Tj(max) = 150 °C. This ensures junction temperature remains below 150 °C with 200 mW per-transistor power dissipation limit.

Can PMP5501Y be used in linear regulator pass elements?

No - it is not rated for linear regulation duty. With only −100 mA IC and −45 V VCEO, it lacks the safe operating area (SOA), thermal robustness, and SOA graph validation required for pass transistor use. It is specified exclusively for small-signal matching applications.

Does the hFE matching specification apply across the full −55 °C to +150 °C range?

No - the hFE1/hFE2 = 0.95–1.00 spec is guaranteed only at Tamb = 25 °C. At −55 °C and +150 °C, matching degrades to ~0.90–1.05 per characterization curves (Fig. 2), so designs requiring tight matching across temperature must include margin or calibration.