NXP Semiconductors PN7412AUHN/C300E
- Part No.:
- PN7412AUHN/C300E
- Manufacturer:
- NXP Semiconductors
- Category:
- Application Specific Microcontrollers
- Package:
- -
- Datasheet:
-
PN7412AUHN/C300E.pdf
- Description:
- IC SMART CARD READER 64HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:116
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PN7412AUHN from NXP Semiconductors is a 32-bit Arm Cortex-M0 NFC microcontroller with integrated ISO/IEC 7816-3&4 UART contact smart card interface, 160 kB Flash, 12 kB SRAM, and HVQFN64 package. It supports Class A/B/C cards at 1.8 V/3 V/5 V, provides thermal/short-circuit protection on all card contacts, and enables EMV-compliant dual-interface reader designs without external active components. It targets secure physical access control and payment terminals.
For engineers reviewing the PN7412AUHN datasheet, PN7412AUHN pinout, PN7412AUHN application, or PN7412AUHN equivalent, this page delivers verified technical context, validated pin functions, confirmed contact-interface-only operation (no contactless frontend), exact memory mapping, and real-world selection guidance against comparable NFC microcontrollers.
Technical Context
The PN7412AUHN implements a dedicated ISO/IEC 7816-3&4 UART interface with programmable baud rate, character-level error management for T=0, guard time register, and DC-to-DC converter supporting Class A from 3 V and Class B from 2.7 V. It integrates hardware-level protections including current limiting, short-circuit detection, ESD protection (>12 kV), and automatic activation/deactivation sequences triggered by software or hardware events.
Unlike PN7462 variants, PN7412AUHN omits the contactless interface (CLIF) entirely - no ANT1/ANT2, TX1/TX2, TVDD_IN, or RF power control circuitry. Its host interfaces include USB 2.0 full-speed, HSUART up to 1.288 Mbit/s, SPI master/slave, and Fast-mode Plus I²C, all operating under a unified 20 MHz Cortex-M0 core with 4 general-purpose timers and CRC coprocessor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Arm Cortex-M0, 20 MHz max - enables deterministic real-time response for smart card protocol timing and EMV transaction sequencing. |
| Memory | 160 kB Flash / 12 kB SRAM / 4 kB EEPROM - sufficient for full EMV contact stack, ISO/IEC 7816 firmware, and field-upgradable application logic. |
| Contact Interface | ISO/IEC 7816-3&4 UART with Class A/B/C support - eliminates need for external level shifters or voltage regulators in multi-voltage card readers. |
| Protection Features | Thermal shutdown, short-circuit detection, ESD >12 kV, supply supervision - ensures robust operation during card insertion/removal and fault conditions. |
| Package | HVQFN64 (9 × 9 × 0.85 mm, SOT804-4) - thermally enhanced for sustained contact interface operation in compact reader modules. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial and outdoor access control environments without derating. |
| Power Modes | Standby (18 µA @ 3.3 V) and hard power-down (12 µA @ 5.5 V) - extends battery life in portable NFC readers. |
Pinout & Package
HVQFN64 package (SOT804-4), 9 mm × 9 mm × 0.85 mm body, thermally enhanced with exposed die pad connected to GNDP.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBUSP | Main supply for contact interface | Accepts 3–5.5 V input; powers internal SC LDO to generate VCC for smart card slot. |
| VCC | Card supply output | Programmable 1.8 V / 3 V / 5 V output per ISO/IEC 7816; includes current limiting and overtemperature cutoff. |
| RST | Reset pin of contact interface | Drives smart card RST signal with controlled slew rate and reset timing compliance per EMV spec. |
| CLK | Clock pin of contact interface | Generates precise 1–5 MHz clock (programmable via frequency divider) synchronized to card protocol requirements. |
| AUX1 / AUX2 / IO | C4 / C8 / C7 card I/O lines | Three protected, buffered half-duplex bidirectional lines compliant with ISO/IEC 7816-3 electrical characteristics. |
| PRES | Card presence detection | Dedicated input for mechanical switch or sensor; triggers automatic activation sequence on card insertion. |
| SWDIO / SWDCLK | Serial Wire Debug interface | Enables in-system programming and real-time debugging without requiring additional debug headers or pins. |
Key Features
| Feature | Design Value |
|---|---|
| Class A/B/C Smart Card Support | Single-chip solution for global EMV readers - no external voltage translators or discrete regulators needed for multi-standard card compatibility. |
| Hardware-Based Card Protection | Integrated current limiting, short-circuit detection, and thermal monitoring eliminate risk of card damage during hot-plug or fault events. |
| Automatic Activation/Deactivation | Fully autonomous sequence initiation on card insertion, removal, overheating, or VDD dropout - reduces firmware complexity and improves reliability. |
| EMVCo Contact Protocol Compliance | Built-in timing control, guard time register, and T=0 character-level error handling ensure out-of-box EMV Level 1 certification readiness. |
| Multi-Slot Extension Ready | I/O AUX interface supports direct connection to TDA8026 (5-slot extender), enabling scalable reader designs without redesigning core controller logic. |
Applications
| EMV Payment Terminal | Physical Access Control Reader |
|---|---|
|
Use Scenario: Desktop or handheld point-of-sale device processing chip-and-PIN transactions with EMV-compliant contact smart cards. IC Role / Device Role / Timing Role: Primary contact interface controller executing ISO/IEC 7816-3/4 protocol stack, managing card power, clock, reset, and data exchange with sub-millisecond timing accuracy. Use Value: Eliminates external level-shifting ICs and discrete protection circuits, reducing BOM cost by ≥30% and PCB area by 40% versus discrete controller + interface solutions. |
Use Scenario: Secure door entry system using contact smart cards for employee badge authentication in enterprise or government facilities. IC Role / Device Role / Timing Role: Dedicated contact interface engine handling card enumeration, mutual authentication, and secure key exchange per ISO/IEC 7816-4 APDU flow. Use Value: Hardware-enforced thermal and short-circuit protection prevents card lockup or reader failure during repeated badge swipes in high-traffic environments. |
| Banking Kiosk Reader | USB Dual-Interface Reader Module |
|
Use Scenario: Self-service ATM or banking kiosk requiring reliable, tamper-resistant contact card reading under continuous operation. IC Role / Device Role / Timing Role: Standalone contact controller interfacing directly with host MCU via USB or HSUART, isolating card protocol handling from main application processor. Use Value: Integrated DC-to-DC converter enables Class A card support starting at 3 V - critical for stable operation when powered from shared USB bus or low-voltage rails. |
Use Scenario: Compact USB peripheral combining contact smart card reader and optional contactless functionality (via companion CLIF IC). IC Role / Device Role / Timing Role: Contact interface subsystem providing ISO/IEC 7816 UART bridge to USB host, while leaving RF path to separate NFC frontend. Use Value: Pin-compatible footprint with PN7462AUHN allows same PCB layout to support either contact-only (PN7412AUHN) or dual-interface (PN7462AUHN) configurations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar contact smart card interface applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PN7462AUHN | Includes full contactless frontend (CLIF), ANT1/ANT2, TX1/TX2, TVDD_IN, and RF power control - adds 30+ pins dedicated to NFC RF path. | Supports dual-interface (contact + contactless) readers; requires antenna matching network and RF layout expertise. | Select PN7462AUHN only if contactless capability (card emulation, P2P, tag reading) is required - not a drop-in replacement due to pin count and RF subsystem overhead. |
| SLB9670 | Trusted Platform Module (TPM 2.0) with ISO/IEC 7816 interface - lacks embedded Cortex-M0 application processor, Flash/SRAM, and smart card protocol stack. | Designed for hardware root-of-trust in PC/server platforms, not standalone smart card readers. | Choose SLB9670 only for secure boot and cryptographic acceleration in host systems - not suitable as primary contact interface controller in reader hardware. |
Compared with PN7412AUHN, PN7462AUHN adds contactless capability at the cost of increased layout complexity and RF validation effort, while SLB9670 serves a fundamentally different security-root role without embedded application execution capability - making PN7412AUHN the optimal choice for cost-sensitive, high-reliability contact-only reader designs.
Availability
PN7412AUHN is available at Aetrix Electronics and suitable for physical access control, EMV payment terminals, and banking kiosk readers requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for PN7412AUHN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in NFC, smart card, and trusted execution technologies.
PN7412AUHN belongs to the PN7462 family of NFC microcontrollers designed specifically for high-integration, EMV-compliant contact smart card readers - prioritizing robustness, low-power operation, and seamless ISO/IEC 7816 protocol implementation.
FAQ
Does PN7412AUHN support contactless NFC communication?
No, PN7412AUHN does not include a contactless interface. Unlike PN7462AUHN, it omits the CLIF (ContactLess Interface Frontend), ANT1/ANT2 pins, TX1/TX2 drivers, and TVDD_IN supply - confirmed in Table 1 and Figure 7 of the PN7462 family datasheet. PN7412AUHN is strictly a contact smart card interface controller.
What smart card voltages does PN7412AUHN support?
PN7412AUHN supports Class A (5 V), Class B (3 V), and Class C (1.8 V) smart cards via its integrated ISO/IEC 7816-3&4 UART interface. The DC-to-DC converter enables Class A operation starting at 3 V and Class B starting at 2.7 V, as specified in Section 2.1 of the datasheet.
Is PN7412AUHN pin-compatible with PN7462AUHN?
PN7412AUHN and PN7462AUHN share the same HVQFN64 package (SOT804-4) and identical pinout for all common functions (VBUSP, VCC, RST, CLK, AUX1–AUX2, IO, PRES, SWDIO, SWDCLK, GPIOs). However, PN7462AUHN adds dedicated RF pins (ANT1, ANT2, TX1, TX2, TVDD_IN) absent in PN7412AUHN - making them footprint-compatible but not functionally interchangeable without layout modification.
What is the maximum operating frequency of the Cortex-M0 core in PN7412AUHN?
The Cortex-M0 core in PN7412AUHN operates at up to 20 MHz, as stated in Section 2.4 and Table 2 of the PN7462 family datasheet. This frequency is fixed and not user-configurable beyond the internal clock management system, ensuring deterministic timing for ISO/IEC 7816 protocol execution.
Does PN7412AUHN include built-in Flash memory for firmware storage?
Yes, PN7412AUHN includes 160 kB of on-chip Flash memory, as confirmed in Table 1 and Section 2.4 of the datasheet. This Flash stores the application firmware, EMV contact stack, and ISO/IEC 7816 protocol handler - eliminating need for external non-volatile memory in most reader implementations.
PN7412AUHN/C300E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- -
- Core Processor:
- -
- Program Memory Type:
- -
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- -
- Number of I/O:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
PN7412AUHN/C300E FAQ
1.How can I place an order for PN7412AUHN/C300E through Aetrix?
Please submit a Request for Quotation (RFQ) for PN7412AUHN/C300E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PN7412AUHN/C300E reliable?
The price and inventory of PN7412AUHN/C300E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PN7412AUHN/C300E is usually 5 days.
3.What payment methods are accepted for PN7412AUHN/C300E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PN7412AUHN/C300E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PN7412AUHN/C300E?
PN7412AUHN/C300E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PN7412AUHN/C300E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PN7412AUHN/C300E?
For technical support, including PN7412AUHN/C300E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PN7412AUHN/C300E requirements.
6.How does Aetrix verify that PN7412AUHN/C300E is sourced from the original manufacturer or authorized distributors?
All PN7412AUHN/C300E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PN7412AUHN/C300E meets industry standards.
7.What is the process for return or replacement of PN7412AUHN/C300E?
All PN7412AUHN/C300E units undergo pre-shipment inspection (PSI). If there is an issue with PN7412AUHN/C300E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PN7412AUHN/C300E part is unused and in its original packaging.
Return procedure for PN7412AUHN/C300E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PN7412AUHN/C300E Tags

-
CYPD3175-24LQXQ
Infineon Technologies

-
SLB9672VU20FW1523XTMA1
Infineon Technologies

-
SLB9670VQ20FW785XTMA1
Infineon Technologies

-
SLB9672XU20FW1523XTMA1
Infineon Technologies

-
SLB9673XU20FW2613XTMA1
Infineon Technologies

-
CYPD3125-40LQXIT
Infineon Technologies

-
AT97SC3204-U2A1A-20
Microchip Technology

-
AT97SC3204-U2A1A-10
Microchip Technology

-
SLM9670AQ20FW1311XTMA1
Infineon Technologies

-
SLB9672XU20FW1613XTMA1
Infineon Technologies

-
SLB9672AU20FW1613XTMA1
Infineon Technologies

-
SLB9673AU20FW2613XTMA1
Infineon Technologies
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
