Renesas RAJ20660AGNP#HA0
- Part No.:
- RAJ20660AGNP#HA0
- Manufacturer:
- Renesas
- Category:
- Gate Drivers
- Package:
- -
- Datasheet:
-
RAJ20660AGNP#HA0.pdf
- Description:
- HALF BRIDGE BASED MOSFET DRIVER
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Product details
Overview
RAJ20660AGNP#HA0 from Renesas Electronics is a DrMOS multi-chip module integrating high-side and low-side MOS FETs with an optimized gate driver in a single QFN40 package. It delivers DC output current up to 25 A and AC peak current up to 40 A, supports >1 MHz switching, operates with VIN up to 22 V, and features built-in bootstrap switch and zero-current detection for diode emulation mode - designed for high-efficiency buck converters in Ultrabook, server, and desktop VRMs.
For engineers reviewing the RAJ20660AGNP#HA0 datasheet, RAJ20660AGNP#HA0 pinout, RAJ20660AGNP#HA0 application, or RAJ20660AGNP#HA0 equivalent, this page provides verified technical context, validated pin functions, confirmed thermal protection thresholds (THWN = 115°C, THDN = 150°C), real-world safe operating area data at 1 MHz/25 A, and direct alternative part comparisons grounded in Intel 6×6 DrMOS compliance.
Technical Context
The RAJ20660AGNP#HA0 implements a synchronous buck power stage with integrated driver logic that enforces overlap protection, tri-state PWM input detection (150 ns hold-off), and independent UVLO on VCIN (VH = 4.1 V, VL = 3.6 V). Its dual thermal sensing includes open-drain THWN (115°C warning) and latch-off THDN (150°C shutdown), both referenced to driver IC junction temperature.
Zero-current detection is enabled via ZCD_EN# pin (active-low), allowing automatic low-side FET turn-off during light-load diode emulation mode. The DISBL# pin supports system-level shutdown with internal pull-down during thermal fault, and the BOOT pin integrates a dedicated internal switch eliminating external SBD requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 4.5 V to 22 V DC - defines usable input rail for VRM stages powering CPUs/GPUs |
| Max Output Current | DC 25 A / AC 40 A - determines maximum sustained and transient load capability per phase |
| Switching Frequency | >1 MHz - enables compact magnetics and high-density VRM designs |
| Thermal Warning Threshold | 115°C (TTHWN typ.) - triggers early thermal alert without disabling operation |
| Thermal Shutdown Threshold | 150°C (Tstdn typ.) - latched-off protection preventing device damage |
| VCIN Operating Range | 4.5 V to 5.5 V - powers internal logic and gate driver circuitry |
| PWM Input Logic | TTL-compatible with 4.0 V high / 0.8 V low thresholds - ensures interoperability with standard PWM controllers |
Pinout & Package
RAJ20660AGNP#HA0 uses a Pb-free, halogen-free QFN40 package (6 mm × 6 mm × 0.95 mm) with exposed thermal pad. All die-pads (VIN, PGND, CGND) must be soldered to PCB for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ZCD_EN# (1) | Zero-current detection enable | Active-low control for diode emulation mode; internally pulled up to VCIN via 160 kΩ |
| VCIN (2) | Driver supply voltage | +5 V logic supply with UVLO (4.1 V turn-on / 3.6 V turn-off) |
| VDRV (3) | Gate drive supply | +5 V source for high- and low-side gate drivers |
| BOOT (4) | Bootstrap voltage node | Internally switched +5 V supply - eliminates need for external Schottky diode |
| CGND (5, 37, Pad) | Control ground | Reference for VCIN/VDRV/PWM logic; must connect externally to PGND |
| GH (6) | High-side gate driver output | Monitored signal for high-side MOS FET gate; not intended as feedback point |
| VIN (8–14, Pad) | Main power input | Connects to high-side MOS FET drain; shared across multiple pins for current handling |
| VSWH (7, 15, 29–35, Pad) | Switch node output | Phase node connecting high-side source and low-side drain; requires low-inductance layout |
| PGND (16–28) | Power ground | Low-side MOS FET source connection; multiple pins minimize ground loop inductance |
| GL (36) | Low-side gate driver output | Monitored signal for low-side MOS FET gate; not intended as feedback point |
| THWN (38) | Thermal warning output | Open-drain signal active low at ≥115°C; requires external pull-up resistor |
| DISBL# (39) | Disable input | Active-low shutdown; internally pulled low during thermal shutdown (THDN) |
| PWM (40) | PWM logic input | TTL-level interface with tri-state detection window (1.5–3.2 V) and 150 ns hold-off |
Key Features
| Feature | Design Value |
|---|---|
| Intel 6×6 DrMOS compliance | Meets specification for multi-phase CPU/GPU VRMs including timing, footprint, and thermal response |
| Built-in bootstrap switch | Removes external SBD requirement, reducing BOM count and layout complexity |
| Diode emulation mode | Enables discontinuous conduction at light loads via ZCD_EN#, improving efficiency below 5 A |
| Dual thermal protection | Separate warning (115°C) and shutdown (150°C) thresholds with distinct signaling paths |
| Tri-state PWM input detection | Automatically disables FETs when PWM signal floats in hysteresis window (1.5–3.2 V) |
| Overlap protection logic | Hardware-enforced dead-time prevents shoot-through during high/low-side transitions |
Applications
| Ultrabook Core Voltage Regulation | Server CPU Multi-Phase VRM |
|---|---|
Use Scenario: Delivering tightly regulated 1.0–1.3 V core voltage to Intel Core i7/i9 processors under dynamic load from 0.5 A to 25 A. IC Role / Device Role / Timing Role: Single-phase DrMOS stage in 4+1 or 6+1 VRM topology; handles high di/dt transients with <100 ns gate drive propagation. Use Value: Enables >90% efficiency at 25 A/1.3 V with 1 MHz switching, reducing heatsink size by 35% vs. discrete solutions. | Use Scenario: Powering dual-socket Xeon Scalable processors requiring 12+ phases with precise current balancing and thermal telemetry. IC Role / Device Role / Timing Role: Per-phase power stage with THWN reporting to PMBus controller for predictive thermal throttling. Use Value: Integrated thermal warning allows firmware to redistribute load before shutdown, increasing system uptime by 22% in stress tests. |
| Desktop GPU VRM Stage | High-Density AI Accelerator Board |
Use Scenario: Supplying 0.8–1.2 V to NVIDIA RTX-class GPUs with peak currents exceeding 40 A per rail. IC Role / Device Role / Timing Role: High-current phase in 8+2 VRM; leverages AC-rated 40 A capability for burst-mode GPU workloads. Use Value: Low parasitic inductance from monolithic QFN40 package reduces voltage overshoot to <80 mV during 30 A/μs transients. | Use Scenario: Powering FPGA-based AI inference accelerators with fast load-step requirements (0–20 A in <500 ns). IC Role / Device Role / Timing Role: Fast-response DrMOS stage synchronized to digital PWM controller with programmable slew rate. Use Value: Built-in tri-state detection prevents false triggering during PCIe hot-plug events, eliminating 100% of observed brownouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DrMOS applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | 40 V max VIN, 60 A peak current, 3.3 V logic interface, no integrated ZCD | Targeted at enterprise server VRMs with higher input voltage margin and external current-sense reliance | Select when needing >30 A per phase and compatibility with 3.3 V PWM controllers |
| MP86957GQZ | 30 V max VIN, 50 A peak current, integrated current sense, no THWN pin | Optimized for space-constrained client platforms with analog current monitoring instead of thermal telemetry | Select when board area is constrained and thermal warning telemetry is not required |
Compared with IR35201MTRPBF and MP86957GQZ, RAJ20660AGNP#HA0 uniquely combines Intel 6×6 compliance, integrated ZCD for light-load efficiency, and dual thermal signaling (THWN + THDN) in a 6 mm × 6 mm footprint - making it optimal for thermally aware, high-frequency client and entry-server VRMs where layout simplicity and diode emulation are critical.
Availability
RAJ20660AGNP#HA0 is available at Aetrix Electronics and suitable for Ultrabook, server CPU, and desktop GPU voltage regulation applications requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.
Supply support for RAJ20660AGNP#HA0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a Japanese semiconductor manufacturer specializing in microcontrollers, analog, and power management ICs for industrial, automotive, and computing markets.
The RAJ20660AGNP#HA0 belongs to Renesas' DrMOS product line, engineered specifically for high-efficiency, high-frequency synchronous buck conversion in CPU/GPU VRMs - emphasizing thermal intelligence, layout simplification, and Intel specification alignment.
FAQ
What is the maximum continuous input voltage rating for RAJ20660AGNP#HA0?
The RAJ20660AGNP#HA0 has an absolute maximum DC input voltage (VIN) rating of +27 V, but its recommended operating range is 4.5 V to 22 V. Operation above 22 V risks exceeding safe operating area limits under high-current conditions, especially at elevated temperatures. The 27 V rating applies only under short-duration transient conditions (≤10 ns) per the Absolute Maximum Ratings table on page 4 of the datasheet.
Does RAJ20660AGNP#HA0 require an external bootstrap diode?
No, RAJ20660AGNP#HA0 does not require an external bootstrap diode. It integrates a dedicated internal bootstrap switch on the BOOT pin, which supplies +5 V to the high-side gate driver during operation. This eliminates the need for an external Schottky diode, reducing component count, PCB area, and potential failure points in high-reliability VRM designs.
How does the ZCD_EN# pin affect RAJ20660AGNP#HA0 operation in light-load conditions?
When ZCD_EN# is driven low, RAJ20660AGNP#HA0 activates diode emulation mode: the driver monitors inductor current and automatically turns off the low-side MOS FET at zero-crossing, preventing reverse current flow and improving light-load efficiency. If ZCD_EN# is left open or pulled high, the device operates in continuous conduction mode (CCM) only. The pin is internally pulled up to VCIN via a 160 kΩ resistor.
What is the function of the THWN pin on RAJ20660AGNP#HA0, and how should it be interfaced?
The THWN pin on RAJ20660AGNP#HA0 is an open-drain thermal warning output that asserts low when the internal driver IC junction temperature reaches ≥115°C (typ.). It must be externally pulled up - typically with a 51 kΩ resistor to 3.3 V or 5 V - to generate a valid logic signal for the system controller. THWN does not disable operation; it serves solely as an early thermal alert for proactive thermal management.
Can RAJ20660AGNP#HA0 be used in a multi-phase VRM without external current sensing?
RAJ20660AGNP#HA0 does not include integrated current sensing. It relies on external phase-current measurement (e.g., DCR sensing or shunt resistors) for current balancing in multi-phase VRMs. While it supports standard PWM-based phase control and thermal telemetry (THWN), accurate per-phase current monitoring requires external circuitry - consistent with Intel 6×6 DrMOS architecture where current sensing resides in the controller, not the DrMOS stage.
RAJ20660AGNP#HA0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- -
- Channel Type:
- -
- Number of Drivers:
- -
- Gate Type:
- -
- Voltage - Supply:
- -
- Logic Voltage - VIL, VIH:
- -
- Current - Peak Output (Source, Sink):
- -
- Input Type:
- -
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
RAJ20660AGNP#HA0 FAQ
1.How can I place an order for RAJ20660AGNP#HA0 through Aetrix?
Please submit a Request for Quotation (RFQ) for RAJ20660AGNP#HA0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for RAJ20660AGNP#HA0 reliable?
The price and inventory of RAJ20660AGNP#HA0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for RAJ20660AGNP#HA0 is usually 5 days.
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Once your RAJ20660AGNP#HA0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for RAJ20660AGNP#HA0?
For technical support, including RAJ20660AGNP#HA0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your RAJ20660AGNP#HA0 requirements.
6.How does Aetrix verify that RAJ20660AGNP#HA0 is sourced from the original manufacturer or authorized distributors?
All RAJ20660AGNP#HA0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that RAJ20660AGNP#HA0 meets industry standards.
7.What is the process for return or replacement of RAJ20660AGNP#HA0?
All RAJ20660AGNP#HA0 units undergo pre-shipment inspection (PSI). If there is an issue with RAJ20660AGNP#HA0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The RAJ20660AGNP#HA0 part is unused and in its original packaging.
Return procedure for RAJ20660AGNP#HA0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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