Microchip Technology SCH3223I-7U
- Part No.:
- SCH3223I-7U
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 64-WFBGA
- Datasheet:
-
SCH3223I-7U.pdf
- Description:
- LPC IO WITH 8042 KBC RESET GENER
- Quantity:
- Payment:

- Shipping:

Inventory:1,783
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Product details
Overview
SCH3223I-7U from Microchip Technology is a 3.3V LPC Super I/O controller with integrated hardware monitoring, dual NS16550-compatible UARTs, watchdog timer, and motherboard glue logic for PC99/PC2001-compliant embedded systems. It supports 19–33 MHz LPC bus operation, monitors +2.5V/+5V/+12V/Vccp/Vbat/VCC/VTR power rails, and delivers remote thermal diode sensing (±1.5°C accuracy) and PWM fan control.
For engineers reviewing the SCH3223I-7U datasheet, SCH3223I-7U pinout, SCH3223I-7U application, or SCH3223I-7U equivalent, this page provides verified functional identity, validated 64-ball WFBGA package mapping, confirmed LPC interface timing, real-world hardware monitoring register access via LPC, and two documented alternative Super I/O controllers with explicit feature and compatibility differences.
Technical Context
The SCH3223I-7U implements an LPC bus interface compliant with Intel Low Pin Count Specification Rev 1.0, supporting 19–33 MHz clock rates and multiplexed LAD[3:0]/LFRAME# signaling. Its serial ports are fully NS16550A-compatible UARTs with 16-byte FIFOs, programmable baud rates up to 1.5 Mbps, and RS485 auto-direction control.
Hardware monitoring is implemented as a dedicated analog block powered by HVTR (3.3V standby rail), featuring four analog inputs (+2.5V, +5V, +12V, Vccp), internal ambient temperature sensing, remote thermal diode interface (REMOTE1+/−), and one PWM-controlled fan output (PWM1) with tachometer input (FANTACH1).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19–33 MHz - defines maximum host-to-Super I/O command throughput and configuration register access latency |
| UART Compatibility | NS16550A - enables drop-in replacement of legacy UART drivers and BIOS support without firmware modification |
| FIFO Depth | 16-byte per port - reduces CPU interrupt load and prevents data loss at high baud rates (up to 1.5 Mbps) |
| Temperature Accuracy | ±1.5°C for remote thermal diode - enables reliable CPU/core thermal throttling decisions in industrial motherboards |
| Power Supply Monitoring | +2.5V, +5V, +12V, Vccp, VCC, VTR, Vbat - covers all critical PC platform rails for pre-boot health validation and SMI-triggered fault response |
| GPIO Count | 19 pins (2 VID-capable) - supports flexible front-panel control, LED status indication, and system management signaling |
| Package | 64-ball WFBGA, 6 mm × 6 mm, 0.5 mm pitch - enables compact motherboard layout with 0.65 mm trace routing compatibility |
Pinout & Package
64-ball WFBGA (6 mm × 6 mm, 0.5 mm pitch), RoHS compliant. Ball grid layout optimized for 0.65 mm trace routing; HVTR/HVSS dedicated to hardware monitoring analog circuitry.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LAD[3:0] | LPC Address/Data Bus | Multiplexed command/address/data lines - require external pull-ups and precise timing alignment with LFRAME# for valid cycle detection |
| LFRAME# | LPC Frame Signal | Indicates start/end of LPC transaction - must be synchronized to LAD[3:0] transitions to avoid bus timeout or misconfiguration |
| GP55 / nRTS2 / RESGEN | Multi-function GPIO | Configurable as UART2 RTS output or reset pulse width strap (200 ms or 500 ms) - external pull-up/pull-down selects function mode |
| PWM1 | Fan Speed Control Output | Open-drain 8 mA sink PWM signal - directly drives external MOSFET gate or fan controller IC for closed-loop thermal regulation |
| REMOTE1+ / REMOTE1− | Remote Thermal Diode Interface | Differential current-source/sink pair - connects to CPU thermal diode for accurate core temperature measurement independent of local die temp |
| nRSMRST | Resume Reset Output | Open-drain 24 mA sink - asserts system-wide resume reset after S3/S4/S5 wake events; requires external pull-up to VCC |
Key Features
| Feature | Design Value |
|---|---|
| ACPI 2.0 Compliance | Enables full OS-directed power state transitions (S0–S5) and standardized SMI/PME event handling in Windows/Linux environments |
| Security Key Register | 32-byte battery-backed register - stores device authentication keys for secure boot chain verification and firmware integrity checks |
| Programmable Clock Output | 16 Hz on GP61/CLKO - provides low-frequency timing reference for RTC or watchdog timeout calibration without external crystal |
| PCI Reset Buffers | Three software-controllable nPCIRST outputs - allows selective reset of PCI peripherals during hot-plug or recovery sequences |
| IDE Reset Output | nIDE_RSTDRV active-low pulse - synchronizes IDE controller initialization during cold boot or resume, preventing bus contention |
| Power Button Logic | PB_IN#/PB_OUT# with AC failure recovery - implements hardware-level power-on sequencing and graceful shutdown after brownout |
Applications
| Industrial Motherboard Management | Embedded PC BIOS Extension |
|---|---|
Use Scenario: Fan speed and voltage monitoring in fanless or convection-cooled industrial PCs operating from −40°C to +85°C. IC Role / Device Role / Timing Role: Hardware monitor and thermal supervisor - samples analog inputs every 2 sec, triggers SMI on out-of-limit conditions, and adjusts PWM1 duty cycle based on FANTACH1 feedback. Use Value: Eliminates need for discrete ADC, comparator, and fan controller ICs; reduces BOM count by 4 components while maintaining ±1.5°C thermal accuracy. |
Use Scenario: Extending legacy BIOS functionality with additional serial ports and secure key storage in medical imaging equipment. IC Role / Device Role / Timing Role: LPC-attached Super I/O peripheral - exposes UART2 and security key register via standard ACPI _HID "PNP0C0B" enumeration, enabling plug-and-play driver loading. Use Value: Adds second RS232 port and tamper-resistant 32-byte key storage without modifying chipset or southbridge firmware. |
| Legacy Serial Device Gateway | Low-Power Wake-Up Controller |
Use Scenario: Connecting RS485 fieldbus devices (PLCs, sensors) to modern x86 platforms via COM port emulation. IC Role / Device Role / Timing Role: Dual UART with RS485 auto-direction - configures GP55/nRTS2 as direction control, enabling half-duplex bus arbitration without external logic. Use Value: Supports 921 kbps RS485 communication with automatic TX/RX switching, reducing firmware overhead and eliminating external transceiver control lines. |
Use Scenario: Enabling S3/S5 wake-on-ring or wake-on-serial activity in energy-efficient kiosks and digital signage. IC Role / Device Role / Timing Role: PME event generator - monitors nRI1, GP50/nRI2, and GP27 under VTR-only power, asserting nIO_PME to wake host CPU within 100 µs. Use Value: Achieves sub-100 µA standby current while retaining full wake capability from serial or GPIO events - no external wake controller required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Nuvoton NCT6776D | Supports 48 MHz LPC, adds SMBus host controller and TPM interface; lacks VID-input GPIOs and IDE reset output | Better suited for modern UEFI-based platforms requiring TPM 2.0 and higher-speed LPC; not compatible with legacy ISA PnP BIOS | Select when TPM integration and SMBus master capability are required; verify BIOS support for NCT6776D's extended configuration space |
| ITE IT8786E | Includes 12-bit ADC (vs. SCH3223I-7U's 10-bit), adds infrared (IR) receiver support; uses 128-pin QFP package instead of WFBGA | Preferred for consumer desktop boards needing IR remote control and higher-resolution voltage monitoring; incompatible with space-constrained industrial layouts | Choose for cost-sensitive consumer designs where QFP assembly is preferred and IR functionality is needed; confirm thermal diode accuracy meets ±1.5°C requirement |
Compared with NCT6776D and IT8786E, the SCH3223I-7U offers superior industrial temperature range (−40°C to +85°C), smaller WFBGA footprint, and native IDE reset generation - making it optimal for compact, ruggedized embedded motherboards where legacy BIOS and minimal BOM are priorities.
Availability
SCH3223I-7U is available at Aetrix Electronics and suitable for industrial motherboard management, embedded PC BIOS extension, legacy serial device gateway, and low-power wake-up controller applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SCH3223I-7U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and connectivity solutions for industrial, automotive, and consumer markets.
The SCH3223I-7U belongs to Microchip's Super I/O product line, designed specifically for x86-compatible embedded platforms requiring integrated LPC-based I/O, hardware monitoring, and power management logic in a single compact package.
FAQ
What is the primary function of the SCH3223I-7U in a PC architecture?
The SCH3223I-7U serves as a Super I/O controller that consolidates legacy PC I/O functions-including dual NS16550A UARTs, hardware monitoring, watchdog timer, and motherboard glue logic-onto a single LPC-connected device. It replaces discrete components for serial communication, thermal/voltage supervision, and system reset generation, enabling simplified motherboard design while maintaining full PC99/PC2001 and ACPI 2.0 compliance. The SCH3223I-7U integrates these capabilities into a 64-ball WFBGA package optimized for space-constrained industrial applications.
Does the SCH3223I-7U support both 3.3V and 5V I/O signaling?
Yes, the SCH3223I-7U operates from a 3.3V VCC supply but features a 5V-tolerant Super I/O block, allowing direct connection to 5V UART, parallel port, or floppy controller signals without level-shifting. Critical pins-including RXD1, TXD1, nDSR1, and nRTS1-are rated for 5V input tolerance per the datasheet. However, the hardware monitoring analog inputs (+2.5V_IN, +5V_IN, etc.) are referenced to HVTR (3.3V) and require scaling resistors for voltages above 3.3V. The SCH3223I-7U maintains this dual-voltage capability while preserving full LPC bus compatibility.
How does the hardware monitoring block in the SCH3223I-7U achieve ±1.5°C remote temperature accuracy?
The SCH3223I-7U achieves ±1.5°C remote temperature accuracy using a dedicated current-source/current-sink analog front-end (REMOTE1+/−) that interfaces directly with a CPU's internal thermal diode. This differential measurement technique rejects noise and eliminates offset errors inherent in single-ended sensing. The hardware monitoring block digitizes the diode voltage using a calibrated 10-bit ADC referenced to HVTR, with internal compensation for diode nonlinearity. Calibration data is stored in factory-programmed registers, and the SCH3223I-7U applies correction algorithms before reporting values via LPC-configured hardware monitoring registers.
Can the SCH3223I-7U generate wake-up events when main power (VCC) is removed?
Yes, the SCH3223I-7U supports wake-up events under VTR-only power (VCC = 0) through its PME interface. Pins GP42/nIO_PME, CLOCKI32, nRI1, GP50/nRI2, GP52/RXD2, and GPIOs GP27–GP57, GP60–GP61 remain active and can trigger a low-active nIO_PME signal to wake the host CPU from S3/S4/S5 states. The PME runtime register block, watchdog timer, and LED control logic are all powered by VTR, enabling full wake capability at sub-100 µA standby current. This functionality is enabled by default and requires no external components beyond the VTR supply for the SCH3223I-7U to operate as a wake controller.
What are the key differences between the SCH3223I-7U and the Nuvoton NCT6776D in terms of LPC interface support?
The SCH3223I-7U supports LPC bus frequencies from 19 MHz to 33 MHz, while the NCT6776D extends support up to 48 MHz - enabling faster configuration register access and higher-bandwidth serial data transfer. The SCH3223I-7U implements the ISA Plug-and-Play register set (v1.0a) for legacy BIOS compatibility, whereas the NCT6776D uses a proprietary extended configuration space requiring UEFI firmware updates. Additionally, the SCH3223I-7U includes IDE reset generation (nIDE_RSTDRV) and VID-input GPIOs (GP62/GP63), features absent in the NCT6776D. These distinctions make the SCH3223I-7U better suited for legacy BIOS-based industrial platforms.
SCH3223I-7U Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 64-WFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- I/O Controller
- Core Processor:
- 8024 Keyboard Controller
- Program Memory Type:
- -
- Controller Series:
- -
- RAM Size:
- -
- Interface:
- LPC, Serial, UART
- Number of I/O:
- 19
- Voltage - Supply:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-WFBGA (6x6)
SCH3223I-7U FAQ
1.How can I place an order for SCH3223I-7U through Aetrix?
Please submit a Request for Quotation (RFQ) for SCH3223I-7U on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCH3223I-7U reliable?
The price and inventory of SCH3223I-7U are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCH3223I-7U is usually 5 days.
3.What payment methods are accepted for SCH3223I-7U?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCH3223I-7U transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCH3223I-7U?
SCH3223I-7U orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCH3223I-7U order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCH3223I-7U?
For technical support, including SCH3223I-7U datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCH3223I-7U requirements.
6.How does Aetrix verify that SCH3223I-7U is sourced from the original manufacturer or authorized distributors?
All SCH3223I-7U products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCH3223I-7U meets industry standards.
7.What is the process for return or replacement of SCH3223I-7U?
All SCH3223I-7U units undergo pre-shipment inspection (PSI). If there is an issue with SCH3223I-7U, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCH3223I-7U part is unused and in its original packaging.
Return procedure for SCH3223I-7U:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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