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Microchip Technology SCH5636-NS
- Part No.:
- SCH5636-NS
- Manufacturer:
- Microchip Technology
- Category:
- Application Specific Microcontrollers
- Package:
- 128-BFQFP
- Datasheet:
-
SCH5636-NS.pdf
- Description:
- DESKTOP EMBEDDED CTRLR 128QFP
- Quantity:
- Payment:
- Shipping:
Inventory:193
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Product details
Overview
SCH5636-NS from Microchip Technology is a 3.3V, ACPI 2.0– and PC2001–compliant Super I/O controller with integrated 32-bit ARC-625D embedded controller, LPC interface (19–33 MHz), 128-pin QFP RoHS package, and hardware monitoring including four PWM fan outputs, four tachometer inputs, PECI 2.0, and dual SMBus 2.0 host controllers - deployed in desktop motherboards for system management, thermal control, and legacy I/O consolidation.
For engineers reviewing the SCH5636-NS datasheet, SCH5636-NS pinout, SCH5636-NS application, or SCH5636-NS equivalent, this page delivers verified technical context on its embedded controller architecture, fan control logic, temperature sensing range (−63°C to +192°C at 0.125°C resolution), voltage monitoring (VBAT/VTR/VCC/Vtt + 1 external), and Super I/O subsystems including dual NS16C550A UARTs, IEEE 1284 EPP/ECP parallel port, and 8042-compatible keyboard/mouse controller.
Technical Context
The SCH5636-NS integrates a high-performance ARC-625D core with 96KB instruction ROM and 16KB dual-ported SRAM, enabling autonomous execution of fan control algorithms, thermal event handling, and SMI-driven power state transitions without host CPU intervention. Its LPC interface supports serial IRQ, PME, and ACPI-compliant wake events, while the embedded controller manages all SMBus and PECI transactions independently during standby.
Hardware monitoring is implemented via a dedicated ADC supporting three remote thermal diodes (including anti-parallel configuration) and internal ambient sensing, coupled with programmable voltage comparators for VBAT, VTR, VCC, Vtt, and one external rail. Fan control uses four independent 16-bit PWM generators with configurable ON/OFF counters and bi-directional PROCHOT# signaling for CPU throttle coordination and forced full-speed operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| LPC Bus Frequency | 19–33 MHz; enables direct, low-latency communication with host chipset while maintaining ACPI 2.0 compliance. |
| Embedded Core | ARC-625D 32-bit processor with 96KB ROM + 16KB dual-ported SRAM; executes firmware for autonomous thermal/fan management and SMI processing. |
| Temperature Sensing | −63°C to +192°C range at 0.125°C resolution; supports up to three external diodes plus internal sensor and PECI/TSI sources. |
| PWM Outputs | Four 16-bit ON/OFF counters; deliver precise, software-programmable duty cycles for discrete fan speed control. |
| Fan Tach Inputs | Four programmable inputs; detect standard tach signals or locked-rotor alarms and trigger speed-fault interrupts. |
| PECI Interface | PECI 2.0 compliant; supports REQUEST#/READY signaling and up to 2 CPUs + 4 domains for Intel platform thermal telemetry. |
| Super I/O Peripherals | Dual NS16C550A UARTs (16-byte FIFO), IEEE 1284 EPP/ECP parallel port, 8042-compatible KBC, and 2.88MB floppy controller; ensures full legacy OS and BIOS compatibility. |
Pinout & Package
Package: 128-pin QFP (3.9 mm footprint), RoHS compliant, with separate VBAT/VTR suspend supply planes and VCC runtime supply sensing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| LPC_AD[0:3] | LPC Address/Data Multiplexed Bus | Carries command, address, and data over shared lines; requires external demultiplexing per LPC specification. |
| LPC_FRAME# | LPC Frame Strobe | Indicates start/end of LPC transaction cycle; synchronizes host-to-device command sequencing. |
| LPC_RST# | LPC Reset Input | Resets LPC interface logic independently of embedded controller core; preserves battery-backed memory contents. |
| PROCHOT# | Bi-directional Thermal Throttle Signal | Asserts to CPU to request throttling; accepts assertions from CPU to trigger SMI or force full PWM output. |
| PWM[0:3] | Pulse Width Modulation Outputs | Drive external fan MOSFETs or fan drivers; each supports independent frequency and duty-cycle programming. |
| TACH[0:3] | Fan Tachometer Inputs | Accept open-collector tach pulses; generate interrupt on speed drop below programmed threshold. |
| SMBCLK/SMBDAT | SMBus 2.0 Clock/Data (Primary) | Supports master/slave operation at up to 400 kHz; fully functional in standby power mode. |
| PECI_CLK/PECI_DATA | PECI 2.0 Interface Signals | Enable bidirectional thermal telemetry with Intel CPUs; support REQUEST#/READY handshake protocol. |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous Fan Control Logic | RRCC (Real-Time Response Curve Control) maps temperature to PWM duty cycle linearly without host CPU involvement. |
| Dual SMBus 2.0 Host Controllers | One controller supports low-voltage SMBus multiplexing; both operate in standby, enabling always-on thermal monitoring. |
| Battery-Backed Resources | 64-byte VBat-backed RAM retains critical status (e.g., power-fail flag) across AC loss and deep sleep states. |
| Glue Logic Integration | Generates RSMRST#, Power OK, speaker output, intrusion detection, and PCI reset signals - eliminating need for discrete logic ICs. |
| ACPI 2.0 Compliance | Supports G0–G3 states, SMI generation, and hardware wake events (keyboard, mouse, timer, thermal) per ACPI specification. |
Applications
| Desktop Motherboard System Management | Legacy I/O Consolidation |
|---|---|
Use Scenario: Integrated platform controller hub companion in ATX desktop motherboards requiring centralized thermal, power, and peripheral control. IC Role / Device Role / Timing Role: Primary Super I/O controller managing fan speed, voltage monitoring, temperature sensing, and SMI-triggered power state transitions. Use Value: Reduces BOM count by integrating UARTs, parallel/serial ports, floppy controller, keyboard/mouse logic, and hardware monitoring into single 128-pin QFP. |
Use Scenario: Replacement for multi-chip legacy I/O solutions in industrial PCs and embedded systems needing IBM PC/AT compatibility. IC Role / Device Role / Timing Role: Unified Super I/O device providing NS16C550A UARTs, IEEE 1284 EPP/ECP parallel port, and 8042-compatible KBC with identical register mapping. Use Value: Maintains full DOS/BIOS/UEFI driver compatibility while adding modern features like PECI, PWM fan control, and battery-backed memory. |
| Intel Platform Thermal Telemetry | Automotive Infotainment Power Management |
Use Scenario: Thermal coordinator in Intel-based systems where CPU die temperature must be read and used to drive fan response. IC Role / Device Role / Timing Role: PECI 2.0 host that retrieves thermal data from up to 2 CPUs and 4 domains, then feeds values to embedded fan control logic. Use Value: Enables accurate, low-overhead CPU temperature acquisition without PCIe or DMI bandwidth consumption - critical for responsive thermal management. |
Use Scenario: Power-aware I/O controller in automotive infotainment head units requiring robust wake-on-event, low-power standby, and voltage fault detection. IC Role / Device Role / Timing Role: System management controller monitoring VBAT, VTR, and VCC rails; generating RSMRST# and Power OK signals during cold crank conditions. Use Value: Supports ASIL-B–aligned power sequencing and fail-safe shutdown via hardware-monitored voltage limits and battery-backed status retention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Super I/O controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IT8786E-S | Integrated 8051 core (not ARC); lacks PECI 2.0; supports only SMBus 1.1; no RRCC fan control algorithm. | Targeted at cost-sensitive consumer boards without Intel CPU thermal telemetry requirements. | Select when PECI is unnecessary and legacy SMBus-only thermal monitoring suffices. |
| NCT6798D | ARM Cortex-M0+ core; higher PWM resolution (8/16-bit selectable); supports AMI BIOS integration but no floppy controller. | Used in modern UEFI platforms where floppy emulation is obsolete and ARM firmware flexibility is prioritized. | Prefer when migrating from legacy BIOS to UEFI and requiring ARM-based firmware extensibility over floppy compatibility. |
Compared with IT8786E-S and NCT6798D, the SCH5636-NS uniquely combines PECI 2.0, RRCC fan control, battery-backed 64-byte memory, and full 2.88MB floppy controller - making it the only option for Intel desktop platforms requiring backward-compatible legacy I/O and real-time CPU thermal telemetry without host CPU polling overhead.
Availability
SCH5636-NS is available at Aetrix Electronics and suitable for desktop motherboard design, industrial PC legacy I/O consolidation, Intel platform thermal telemetry, automotive infotainment power sequencing, and ACPI-compliant system management requiring stable component supply across long-lifecycle programs.
Supply support for SCH5636-NS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, and connectivity solutions, with broad expertise in embedded control and system-level integration.
The SCH5636-NS belongs to Microchip's Super I/O product line, designed specifically for PC-class platforms requiring ACPI-compliant system management, hardware monitoring, and legacy peripheral consolidation in a single chip.
FAQ
What is the primary function of the SCH5636-NS in a desktop motherboard?
The SCH5636-NS serves as the central Super I/O controller, integrating hardware monitoring (temperature, voltage, fan speed), fan control (four PWM outputs with RRCC algorithm), legacy peripherals (dual UARTs, parallel port, keyboard/mouse controller, floppy controller), and system management (ACPI 2.0, SMI, PECI 2.0). It operates autonomously via its ARC-625D embedded core to reduce host CPU load and enable responsive thermal and power management in desktop platforms.
Does the SCH5636-NS support PECI 2.0, and what does that enable?
Yes, the SCH5636-NS implements a full PECI 2.0 interface with REQUEST# and READY signaling, supporting up to two CPUs and four thermal domains. This enables direct, low-latency acquisition of Intel CPU die temperatures without host CPU intervention - a critical capability for real-time fan control, thermal throttling coordination via PROCHOT#, and platform-level thermal telemetry in modern desktop and workstation systems using the SCH5636-NS.
How many fan control channels does the SCH5636-NS provide, and what is their precision?
The SCH5636-NS provides four independent PWM outputs, each controlled by a 16-bit ON counter and 16-bit OFF counter for fine-grained duty-cycle resolution. Combined with the RRCC (Real-Time Response Curve Control) algorithm, these outputs deliver linear, temperature-proportional fan speed control without host CPU involvement - essential for silent, responsive thermal management in systems using the SCH5636-NS.
What legacy I/O functions are integrated into the SCH5636-NS?
The SCH5636-NS integrates a complete set of legacy PC I/O: two NS16C550A-compatible UARTs with 16-byte FIFOs, an IEEE 1284 EPP/ECP parallel port, an 8042-compatible keyboard/mouse controller with 2 KB ROM and 256 bytes RAM, and a licensed 2.88 MB floppy disk controller compatible with CMOS 765B and IBM PC/AT standards - all accessible via standard BIOS and OS drivers, ensuring full backward compatibility in systems deploying the SCH5636-NS.
Is the SCH5636-NS RoHS compliant, and what package does it use?
Yes, the SCH5636-NS is RoHS compliant and packaged in a 128-pin QFP with a 3.9 mm footprint, as confirmed in Microchip's DS00001732A datasheet. The "NS" suffix explicitly denotes this RoHS-compliant QFP variant, and the device supports dual suspend supply planes (VBAT and VTR) alongside runtime VCC sensing - key for "instant-on" functionality and robust power management in designs using the SCH5636-NS.
SCH5636-NS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 128-BFQFP
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Networking and Communications
- Core Processor:
- ARC-625D
- Program Memory Type:
- ROM (96KB)
- Controller Series:
- -
- RAM Size:
- 16K x 8
- Interface:
- ACPI, BC-Link, I2C/SMBus, LPC, PECI, PS/2, SPI
- Number of I/O:
- 60
- Voltage - Supply:
- 2.97V ~ 3.63V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 128-PQFP (14x20)
SCH5636-NS FAQ
1.How can I place an order for SCH5636-NS through Aetrix?
Please submit a Request for Quotation (RFQ) for SCH5636-NS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SCH5636-NS reliable?
The price and inventory of SCH5636-NS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SCH5636-NS is usually 5 days.
3.What payment methods are accepted for SCH5636-NS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SCH5636-NS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SCH5636-NS?
SCH5636-NS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SCH5636-NS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SCH5636-NS?
For technical support, including SCH5636-NS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SCH5636-NS requirements.
6.How does Aetrix verify that SCH5636-NS is sourced from the original manufacturer or authorized distributors?
All SCH5636-NS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SCH5636-NS meets industry standards.
7.What is the process for return or replacement of SCH5636-NS?
All SCH5636-NS units undergo pre-shipment inspection (PSI). If there is an issue with SCH5636-NS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SCH5636-NS part is unused and in its original packaging.
Return procedure for SCH5636-NS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SCH5636-NS Tags
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