Skyworks Solutions Inc. SI3460-E02-GM
- Part No.:
- SI3460-E02-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Power Over Ethernet (PoE) Controllers
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
SI3460-E02-GM.pdf
- Description:
- IC POE CNTRL 1 CHANNEL 11QFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,497
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI3460-E02-GM from Silicon Laboratories is an IEEE 802.3af-compliant single-port Power Sourcing Equipment (PSE) interface and DC-DC controller for PoE endpoint/midspan applications. It integrates a digital PWM-based –48 V dc-dc converter, supports robust 3-point PD detection, IEEE-compliant classification (Class 0–4), and autonomous operation without host processor control. It delivers up to 15.4 W output power with input UVLO at 10 V and operates across –40 to +85 °C.
For engineers reviewing the SI3460-E02-GM datasheet, SI3460-E02-GM pinout, SI3460-E02-GM application, or SI3460-E02-GM equivalent, key selection considerations include its 11-pin QFN (3 × 3 mm) package, classification-based current limiting, LED status signaling (detect/power good/fault), 250 kHz PWM frequency, and support for both endpoint and midspan configurations via STATUS pin voltage programming.
Technical Context
The SI3460-E02-GM implements a fully autonomous PSE state machine with integrated detection (3-point resistance sensing), classification (current-measured Class 0–4 assignment), disconnect (7.5 mA threshold, 350 ms hold time), and protection (UVLO, short-circuit, overload timing). Its digital PWM dc-dc controller generates –48 V output directly from 11–16 V input using external FETs and magnetics.
Pin-programmable configuration via STATUS pin voltage sets operating mode (endpoint/midspan), supported power level (4 W to 15.4 W), class range, and fault restart behavior (auto-restart after 2 s or reset-triggered). All functions-including GATE drive, CTRL1/CTRL2 PWM averaging, 250 kHz clock generation, and analog sensing (ISENSE, VSENSE, DETA)-are self-contained with no firmware or host interface required.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| IEEE Compliance | Fully compliant with IEEE 802.3af for detection, classification, disconnect, and power delivery-no external logic or timing adjustments needed. |
| Output Voltage | –46 V to –54 V (typ. –50 V) at VOUT; enables SELV-compatible telephony interface integration with standard PoE magnetics. |
| Input Supply Range | 11 V to 16 V on VIN; operates directly from isolated +12 V or +15 V supply-no auxiliary regulator required. |
| Detection Algorithm | Robust 3-point signature resistance measurement (15–33 kΩ window) eliminates false detection from capacitive loads or noise. |
| Classification Support | Supports all IEEE 802.3af classes (0–4); current-sense-based classification at ISENSE determines power grant per configured class limits. |
| Thermal Range | –40 °C to +85 °C ambient operating temperature; thermal impedance θJA = 75 °C/W enables compact PCB layout without forced airflow. |
| Efficiency | 75% typical system efficiency (VIN to VOUT); reduces heat dissipation in space-constrained embedded PSE designs. |
Pinout & Package
SI3460-E02-GM uses an 11-pin Quad Flat No-Lead (QFN) package with 3 × 3 mm footprint, Pb-free and RoHS-compliant. Exposed thermal pad on underside improves thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GATE | Digital output | Drives external high-side PSE pass FET (M2); logic low enables –48 V output; requires gate driver stage per reference design. |
| CTRL1 / CTRL2 | Digital outputs | Averaged PWM outputs controlling dc-dc converter duty cycle; also generate detection voltages during signature sensing phase. |
| 250KHZ | Digital output | Fixed 250 kHz square wave (50% duty) filtered into triangular waveform for dc-dc control loop; gated off during detection/classification. |
| DETA | Analog input | Null detector input for resistive bridge during 3-point PD signature measurement; critical for accurate RDETmin/RDETmax validation. |
| VSENSE | Analog input | Feedback input for –48 V output regulation; 0.930 V at VSENSE corresponds to –50 V at VOUT per internal scaling. |
| ISENSE | Analog input | Current sense input for classification and overload monitoring; connects to shunt resistor to measure output current for class assignment and ICUT/ILIM enforcement. |
| STATUS | Analog in / Digital out | Configures mode (endpoint/midspan), class support, and fault restart behavior at power-up via resistor-divider voltage; also drives LED status indicator. |
| RST | Digital input | Active-low reset; forces inactive state (PWM off, M2 off) and resets state machine-used for manual recovery or system-level fault handling. |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous PSE Operation | No host processor, firmware, or external timing components required-full IEEE 802.3af compliance implemented in hardware state machine. |
| Programmable Classification Power Level | STATUS pin voltage selects supported class range (e.g., 15.4 W for Class 0/3/4 or 4 W for Class 1 only), enabling BOM optimization per application need. |
| Integrated Protection Logic | Combines input UVLO (10 V turn-off), classification-based current limiting, short-circuit shutdown, and disconnect hysteresis-reduces external protection component count. |
| LED Status Signaling | Single STATUS pin drives LED with distinct blink patterns: 3 Hz during detection, steady-on during power delivery, 10 Hz rapid flash for faults (UVLO, overcurrent, class mismatch). |
| Midspan/Endpoint Dual Mode | Pin-configurable timing (e.g., 2 s vs. 250 ms disconnect backoff) satisfies IEEE 802.3af requirements for both midspan injectors and endpoint switches without redesign. |
Applications
| VoIP Endpoint Switches | FTTH Media Converters |
|---|---|
|
Use Scenario: Embedded 4-port VoIP switch powering IP phones over Ethernet cabling in enterprise or SMB environments. IC Role / Device Role / Timing Role: SI3460-E02-GM acts as autonomous PSE controller managing detection, classification, and –48 V power delivery per port with no CPU involvement. Use Value: Enables cost-effective, space-efficient PoE implementation with full IEEE 802.3af compliance and thermal operation up to +85 °C in fanless enclosures. |
Use Scenario: Fiber-to-the-home media converter delivering PoE to wireless access points or surveillance cameras at customer premises. IC Role / Device Role / Timing Role: SI3460-E02-GM serves as single-port PSE interface generating SELV-compatible –48 V output from 12 V input, supporting midspan timing for interoperability with legacy PDs. Use Value: Eliminates need for external microcontroller or timing IC while meeting strict isolation and safety requirements for residential deployment. |
| Cable Modem Gateways | Set-Top Box PoE Ports |
|
Use Scenario: Integrated cable modem/router with built-in PoE port to power MoCA adapters or Wi-Fi extenders via Ethernet. IC Role / Device Role / Timing Role: SI3460-E02-GM provides autonomous, classification-aware PSE functionality with configurable power level (e.g., Class 2 for 7 W) to match downstream device requirements. Use Value: Reduces bill-of-materials by integrating dc-dc control and PSE logic into one IC, minimizing PCB area and qualification effort for consumer-grade devices. |
Use Scenario: Advanced set-top box with PoE-enabled HDMI extender or IR blaster module powered over spare Ethernet pairs. IC Role / Device Role / Timing Role: SI3460-E02-GM functions as endpoint-mode PSE with auto-restart on fault, delivering stable –48 V output with inrush current control and disconnect detection. Use Value: Supports reliable hot-plug operation and seamless reconnection of accessories without requiring user intervention or system reboot. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PSE controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si3462-A02-GM | Successor device with enhanced ESD tolerance (±4 kV HBM), improved efficiency (>80%), and extended classification accuracy across temperature; pin-compatible but requires updated layout for thermal pad. | Recommended for new designs requiring higher reliability, lower power loss, or broader environmental qualification (e.g., industrial outdoor gateways). | Select Si3462-A02-GM for new designs-Silicon Labs explicitly states SI3460-E02-GM is not recommended for new designs and cites Si3462 as the replacement path. |
| TPS23753APWPR | Analog-based PSE controller with external MOSFET drivers; lacks integrated dc-dc controller-requires separate –48 V supply or external flyback controller. | Suitable where system already includes isolated –48 V rail or where analog control loop tuning is preferred over digital PWM autonomy. | Choose TPS23753APWPR only if leveraging existing –48 V infrastructure or requiring TI's analog PSE ecosystem (e.g., companion PD controllers like TPS23750). |
Compared with SI3460-E02-GM, Si3462-A02-GM offers higher efficiency and updated robustness for new designs, while TPS23753APWPR provides analog flexibility but demands external power conversion-making SI3460-E02-GM optimal for cost-sensitive, self-contained embedded PSEs where digital autonomy and integrated dc-dc control are prioritized.
Availability
SI3460-E02-GM is available at Aetrix Electronics and suitable for VoIP endpoint switches, FTTH media converters, cable modem gateways, and set-top box PoE ports requiring stable component supply and long-term industrial lifecycle support.
Supply support for SI3460-E02-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Silicon Laboratories is a fabless semiconductor company specializing in timing, IoT, and connectivity solutions, with deep expertise in mixed-signal IC design and energy-efficient system integration.
The SI3460-E02-GM belongs to Silicon Labs' Power-over-Ethernet (PoE) PSE controller product line, designed specifically for cost-optimized, autonomous, single-port embedded PSE implementations in endpoint and midspan equipment.
FAQ
What is the primary function of the SI3460-E02-GM in a PoE system?
The SI3460-E02-GM serves as a fully autonomous IEEE 802.3af-compliant Power Sourcing Equipment (PSE) controller and DC-DC converter. It manages PD detection, classification, power delivery, and protection-generating –48 V output directly from a 12 V or 15 V input without host processor involvement. Its role in the SI3460-E02-GM-based system is to eliminate external timing, control, or firmware dependencies while ensuring full standards compliance.
Does the SI3460-E02-GM require external firmware or a microcontroller to operate?
No, the SI3460-E02-GM operates completely autonomously. Its internal state machine handles all IEEE 802.3af functions-including 3-point detection, classification, disconnect, and protection-without firmware, software, or host processor interface. Configuration is achieved solely through passive components (e.g., STATUS pin resistor divider), making the SI3460-E02-GM ideal for resource-constrained embedded systems.
How does the SI3460-E02-GM support both endpoint and midspan PSE configurations?
The SI3460-E02-GM supports both modes via programmable STATUS pin voltage, which configures timing parameters including disconnect backoff delay (250 ms for endpoint, 2 s for midspan) and restart behavior. This eliminates the need for separate part numbers or board revisions-enabling one SI3460-E02-GM design to serve dual applications with only minor external resistor changes.
What protection features are integrated into the SI3460-E02-GM?
The SI3460-E02-GM integrates input undervoltage lockout (UVLO at 10 V), classification-based current limiting, output short-circuit protection, overload timing (60 ms timeout), and disconnect hysteresis. These protections are enforced in hardware without external components-ensuring robust operation during fault conditions while maintaining IEEE 802.3af compliance throughout the SI3460-E02-GM's operational life.
Is the SI3460-E02-GM still recommended for new designs?
No-Silicon Labs explicitly states "Not Recommended for New Designs" and recommends the SI3462 as the replacement. The SI3460-E02-GM remains available for legacy support and existing production, but new designs should use SI3462-A02-GM for improved efficiency, ESD tolerance, and long-term roadmap alignment. Aetrix Electronics maintains inventory of SI3460-E02-GM for continuity, but advises migration planning for future projects.
SI3460-E02-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Controller (PSE), DC/DC
- Number of Channels:
- 1
- Power - Max:
- 15.4 W
- Internal Switch(s):
- No
- Auxiliary Sense:
- Yes
- Standards:
- 802.3af (PoE)
- Voltage - Supply:
- 11V ~ 16V
- Current - Supply:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 11-QFN (3x3)
SI3460-E02-GM FAQ
1.How can I place an order for SI3460-E02-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI3460-E02-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI3460-E02-GM reliable?
The price and inventory of SI3460-E02-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI3460-E02-GM is usually 5 days.
3.What payment methods are accepted for SI3460-E02-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI3460-E02-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI3460-E02-GM?
SI3460-E02-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI3460-E02-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI3460-E02-GM?
For technical support, including SI3460-E02-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI3460-E02-GM requirements.
6.How does Aetrix verify that SI3460-E02-GM is sourced from the original manufacturer or authorized distributors?
All SI3460-E02-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI3460-E02-GM meets industry standards.
7.What is the process for return or replacement of SI3460-E02-GM?
All SI3460-E02-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI3460-E02-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI3460-E02-GM part is unused and in its original packaging.
Return procedure for SI3460-E02-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI3460-E02-GM Tags

-
TPS2378DDAR
Texas Instruments

-
TPS23753APWR
Texas Instruments

-
TPS23756PWPR
Texas Instruments

-
TPS23750PWPR
Texas Instruments

-
MP8007GV-Z
Monolithic Power Systems Inc.

-
TPS23861PWR
Texas Instruments

-
TPS23753PWR
Texas Instruments

-
PD69201ILD-TR
Microchip Technology

-
SI3402-B-GM
Skyworks Solutions Inc.

-
SI3402-B-GMR
Skyworks Solutions Inc.

-
SI34071-A01-GMR
Skyworks Solutions Inc.

-
SI3404-A-GMR
Skyworks Solutions Inc.
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
