Infineon Technologies SLB9670VQ12FW641XUMA1

Overview

SLB9670VQ12FW641XUMA1 from Infineon is a TPM 1.2-compliant Trusted Platform Module implementing hardware-based root-of-trust for secure boot, cryptographic key storage, and platform integrity verification. It features SPI interface (up to 43 MHz), 24 PCRs, 6 kByte NV memory, and operates in standard temperature range (-20°C to +85°C) in PG-VQFN-32-13 package. Used in Chromebook/Chromebox platforms for firmware validation and attestation.

For engineers reviewing the SLB9670VQ12FW641XUMA1 datasheet, SLB9670VQ12FW641XUMA1 pinout, SLB9670VQ12FW641XUMA1 application, or SLB9670VQ12FW641XUMA1 equivalent, key selection factors include TPM 1.2 compliance level, SPI timing constraints, low-power standby current (110 μA), GPIO/PP pin configuration for physical presence control, and CC EAL4+ certification status.

Technical Context

The SLB9670VQ12FW641XUMA1 implements TCG TPM Main Specification v1.2 Rev. 116 with internal power management that auto-enters low-power state post-transaction and wakes on SPI activity. It supports only SPI Mode 0 with strict timing requirements (tSU, tH, tCYC ≤ 23.3 ns min).

It integrates 8 monotonic counters, 16 key slots (2048-bit RSA), and 1280 Byte I/O buffer - all accessible via standardized TPM command/response protocol over SPI. The PIRQ# pin provides active-low interrupt signaling with open-drain output and no internal pull-up.

Key Specifications

Pinout & Package

SLB9670VQ12FW641XUMA1 uses PG-VQFN-32-13: 5 mm × 5 mm, 0.5 mm pitch, exposed thermal pad, RoHS-compliant package with wettable flanks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TPM 1.2 security module applications.

Compared with SLB9670XQ12FW641XUMA1, the SLB9670VQ12FW641XUMA1 trades extended temperature tolerance for cost and footprint efficiency in commercial laptops; versus SLB9673VQ20, it offers proven TPM 1.2 compatibility with minimal integration effort but lacks modern algorithm support and scalability.

Availability

SLB9670VQ12FW641XUMA1 is available at Aetrix Electronics and suitable for Chromebook manufacturing, industrial PLC security upgrades, and medical imaging appliance BOMs requiring stable component supply and long-term lifecycle assurance.

Supply support for SLB9670VQ12FW641XUMA1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, sensing, and security ICs, with global R&D and wafer fabrication infrastructure.

The OPTIGA™ TPM product line delivers certified, standards-compliant hardware security modules designed specifically for platform integrity, secure boot, and trusted identity in client, industrial, and medical endpoints.

FAQ

What is the maximum SPI clock frequency supported by SLB9670VQ12FW641XUMA1?

The device supports SPI clock frequencies up to 43 MHz under TCG-specified timing constraints (tCYC ≥ 23.3 ns). This is verified in Section 4.4 AC Characteristics of the datasheet, where setup/hold times are defined for SCLK, CS#, MOSI, and MISO. Exceeding this frequency risks command corruption or timeout errors due to internal state machine timing margins.

Does SLB9670VQ12FW641XUMA1 require external pull-up resistors on any pins?

Yes - the PIRQ# pin (Pin 18) requires an external pull-up resistor because it is open-drain with no internal pull-up. The RST# pin (Pin 17) has a weak internal pull-up and may operate without external bias, but a 10 kΩ external pull-up is recommended for noise immunity in noisy board environments. PP and GPIO pins have internal pull-down and pull-up respectively, making external resistors optional.

How is physical presence (PP) pin functionality implemented in SLB9670VQ12FW641XUMA1?

The PP pin (Pin 7) is a dedicated hardware input tied to jumper position: grounded for standard operation, pulled to VDD to unlock privileged commands like TPM_ForceClear. It has an internal pull-down resistor, so floating defaults to GND logic. This design enforces out-of-band authorization for destructive operations - preventing remote exploitation while enabling field service via physical access.

Is SLB9670VQ12FW641XUMA1 compatible with Linux kernel's built-in TPM driver?

Yes - the device is supported by the upstream Linux kernel tpm_tis_spi driver since v4.12. It enumerates as a standard SPI-TIS TPM 1.2 device, enabling full /dev/tpm0 access for userspace tools (tpm-tools, trousers, tpm2-tss). No vendor-specific firmware or patches are required, and kernel logs confirm "tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x1B, rev-id 16)" on enumeration.