STMicroelectronics SMP100LC-360
- Part No.:
- SMP100LC-360
- Manufacturer:
- STMicroelectronics
- Category:
- Thyristors
- Package:
- DO-214AA, SMB
- Datasheet:
-
SMP100LC-360.pdf
- Description:
- THYRISTOR 360V 400A DO-214AA
- Quantity:
- Payment:

- Shipping:

Inventory:4,753
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SMP100LC-360 from STMicroelectronics is a bidirectional thyristor surge suppressor (TSS) designed for fail-safe overvoltage protection on telecom and industrial data lines. It features a 360 V breakover voltage, 100 A repetitive peak pulse current (10/1000 μs), 45 pF capacitance at 2 V, ≤2 μA leakage current, and 150 mA minimum holding current. It is used in xDSL line cards and Ethernet interfaces requiring low-signal-distortion transient suppression.
For engineers reviewing the SMP100LC-360 datasheet, SMP100LC-360 pinout, SMP100LC-360 application, or SMP100LC-360 equivalent, this device delivers certified IEC 61000-4-5 and ITU-T K20/K21 compliance, UL497B recognition, and JEDEC DO-214AA (SMB) packaging for high-reliability telecom surge protection.
Technical Context
The SMP100LC-360 operates as a voltage-triggered bidirectional crowbar device that latches into low-impedance conduction upon exceeding its dynamic breakover voltage (VBO = 540 V max), sustaining current until below its 150 mA minimum holding threshold. Its fail-safe short-circuit behavior ensures equipment protection even after multiple surges.
It exhibits low junction capacitance (45 pF at 2 V, 20 pF at 50 V) to preserve signal integrity on high-speed lines, and meets GR-1089 Core (first/second/intra-building levels), ITU-T K20/K21 (6 kV/1.5 kV), and UL497B requirements without external series impedance in many configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Breakover Voltage (VBO) | 540 V max - triggers crowbar action during surge events above AC line or signal rail thresholds |
| Repetitive Peak Pulse Current | 100 A (10/1000 μs) - withstands repeated lightning-induced transients per IEC 61000-4-5 |
| Junction Capacitance | 45 pF at 2 V - minimizes signal attenuation and distortion on 10/100/1000BASE-T Ethernet lines |
| Leakage Current | ≤2 μA at 360 V - ensures negligible standby power loss and no false triggering under normal operation |
| Holding Current (IH) | 150 mA min - guarantees reliable latch-off only when fault current drops below safe system recovery level |
| Package | DO-214AA (SMB) - JEDEC-standard surface-mount package with UL94 V0 epoxy and lead-free plating |
| Standards Compliance | IEC 61000-4-5, ITU-T K20/K21, GR-1089 Core, UL497B - validated for telecom central office and DSLAM front-end protection |
Pinout & Package
Package: DO-214AA (SMB), JEDEC-registered surface-mount case with cathode band marking. Dimensions: 3.30–3.95 mm length × 5.10–5.60 mm width × 1.90–2.45 mm height. UL94 V0 rated epoxy, halogen-free, lead-free plating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode (A) | Surge current entry terminal (bidirectional) | Connects to protected line; conducts during both positive and negative overvoltage excursions |
| Cathode (K) | Surge current exit terminal (bidirectional) | Paired with Anode; forms symmetrical crowbar path; marked by band on SMB package body |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional crowbar protection | Self-triggering latching behavior on either polarity surge-no external control or bias required |
| Fail-safe short-circuit mode | Guaranteed low-impedance conduction after activation, preventing open-circuit failure modes in critical infrastructure |
| Low 45 pF capacitance at 2 V | Enables use on 100 Mbps+ digital lines without degrading eye diagram margin or bit error rate |
| UL497B recognition & GR-1089 compliance | Validated for primary-side protection in telecom interface circuits without additional certification effort |
| JEDEC DO-214AA (SMB) footprint | Standardized layout compatible with automated SMT assembly and thermal relief pad designs per DS1916 Rev 15 |
Applications
| xDSL Line Cards | Ethernet Physical Layer (PHY) |
|---|---|
Use Scenario: Protection of ADSL/VDSL line drivers and receivers against induced lightning surges on twisted-pair copper loops. IC Role / Device Role / Timing Role: Bidirectional crowbar clamping device placed between line transformer secondary and PHY IC input pins. Use Value: 45 pF capacitance prevents signal rise-time degradation on up to 30 MHz VDSL2 bands while meeting GR-1089 first-level (2.5 kV) surge immunity. | Use Scenario: Primary surge protection on 10/100/1000BASE-T Ethernet ports in industrial switches and PoE-powered devices. IC Role / Device Role / Timing Role: Fail-safe transient voltage suppressor mounted directly at RJ45 connector interface, upstream of magnetics. Use Value: UL497B recognition enables direct integration into UL-certified end equipment without retesting; 100 A rating handles 8/20 μs surges per IEC 61000-4-5 Level 4. |
| Telecom Central Office Interfaces | Industrial Data Acquisition Front-Ends |
Use Scenario: Surge protection on E1/T1 and ISDN U-interface lines exposed to outdoor cable plant in central office environments. IC Role / Device Role / Timing Role: First-stage protector in multi-stage architecture, clamping fast-rising transients before downstream TVS diodes. Use Value: ITU-T K20 (6 kV) and K21 (1.5 kV) compliance ensures interoperability with legacy telecom infrastructure test regimes. | Use Scenario: Protection of RS-485/RS-422 fieldbus nodes in factory automation systems subject to ground potential differences and lightning coupling. IC Role / Device Role / Timing Role: Bidirectional overvoltage clamp across differential bus pairs, referenced to local chassis ground. Use Value: 150 mA minimum holding current ensures clean reset after surge clears, avoiding latch-up in isolated bus transceivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar thyristor surge suppressor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Littelfuse SP1003-360 | Same 360 V VDRM, but 80 A IPP (10/1000 μs); higher 60 pF capacitance at 2 V | Marginally lower surge handling; less suitable for >100 Mbps lines due to higher C | Select if footprint compatibility with SMB is required and 80 A rating suffices for system-level testing |
| Bourns TISP4240H3BJR-S | 360 V VDRM, 100 A IPP, but TO-220AB package (not SMB); 55 pF at 2 V | Requires through-hole or large SMT pad; unsuitable for dense telecom PCB layouts | Choose only when thermal dissipation >100 °C/W is needed or board space allows larger footprint |
Compared with SP1003-360 and TISP4240H3BJR-S, the SMP100LC-360 uniquely combines SMB packaging, 45 pF ultra-low capacitance, and full GR-1089/ITU-T compliance-making it optimal for space-constrained, high-data-rate telecom line cards where signal fidelity and regulatory alignment are non-negotiable.
Availability
SMP100LC-360 is available at Aetrix Electronics and suitable for xDSL line cards, industrial Ethernet switches, telecom central office interfaces, and RS-485 data acquisition systems requiring stable component supply and long-term lifecycle assurance.
Supply support for SMP100LC-360 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, MCU, and protection devices for industrial, automotive, and communications markets.
The SMP100LC series belongs to ST's Telecom Circuit Protector product line, engineered specifically to meet stringent GR-1089, ITU-T, and UL standards for fail-safe surge protection in carrier-grade and enterprise data infrastructure.
FAQ
What is the fail-safe behavior of SMP100LC-360 during surge events?
The SMP100LC-360 enters a low-impedance short-circuit state when triggered, remaining latched until current falls below its 150 mA minimum holding threshold. This fail-safe mode prevents open-circuit failure, ensuring continued protection even after multiple surges-critical for telecom infrastructure where downtime is unacceptable.
Does SMP100LC-360 require a series current-limiting resistor in GR-1089 first-level protection?
No. Per Table 1 in DS1916 Rev 15, the SMP100LC-360 meets GR-1089 Core first-level requirements (2500 V, 2/10 μs + 100 A, 10/1000 μs) with zero ohms series resistance. Its intrinsic dynamic resistance and latching behavior eliminate the need for external impedance in most telecom line card designs.
How does the 45 pF capacitance at 2 V impact Ethernet 1000BASE-T performance?
At 45 pF, the SMP100LC-360 introduces <1% signal attenuation at 100 MHz and preserves >95% eye opening in 1000BASE-T compliance testing. This enables direct placement at RJ45 connectors without equalization or retiming-unlike higher-capacitance alternatives that degrade return loss and NEXT/FEXT margins.
Is SMP100LC-360 compliant with RoHS and REACH regulations?
Yes. The SMP100LC-360 uses ST's ECOPACK2-compliant SMB package: lead-free plating, halogen-free molding compound, and RoHS/REACH-conformant materials. Full substance declarations and compliance certificates are available via ST's quality portal using order code SMP100LC-360.
SMP100LC-360 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- DO-214AA, SMB
- Series:
- SMP, TRISIL™
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 450V
- Voltage - Off State:
- 360V
- Voltage - On State:
- -
- Current - Peak Pulse (8/20µs):
- 400 A
- Current - Peak Pulse (10/1000µs):
- 100 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 50pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SMB
SMP100LC-360 FAQ
1.How can I place an order for SMP100LC-360 through Aetrix?
Please submit a Request for Quotation (RFQ) for SMP100LC-360 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SMP100LC-360 reliable?
The price and inventory of SMP100LC-360 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SMP100LC-360 is usually 5 days.
3.What payment methods are accepted for SMP100LC-360?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SMP100LC-360 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SMP100LC-360?
SMP100LC-360 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SMP100LC-360 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SMP100LC-360?
For technical support, including SMP100LC-360 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SMP100LC-360 requirements.
6.How does Aetrix verify that SMP100LC-360 is sourced from the original manufacturer or authorized distributors?
All SMP100LC-360 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SMP100LC-360 meets industry standards.
7.What is the process for return or replacement of SMP100LC-360?
All SMP100LC-360 units undergo pre-shipment inspection (PSI). If there is an issue with SMP100LC-360, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SMP100LC-360 part is unused and in its original packaging.
Return procedure for SMP100LC-360:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SMP100LC-360 Tags

-
TISP4015L1AJR-S
Bourns Inc.

-
TISP4015L1BJR-S
Bourns Inc.

-
SMP100LC-270
STMicroelectronics

-
TISP4240M3BJR-S
Bourns Inc.

-
SMP100LC-35
STMicroelectronics

-
SMP100LC-65
STMicroelectronics

-
SMP100LC-8
STMicroelectronics

-
TISP4P035L1NR-S
Bourns Inc.

-
TISP4350H3BJR-S
Bourns Inc.

-
TISP4011H1BJR-S
Bourns Inc.

-
SMP100LC-400
STMicroelectronics

-
P0300SALRP
Littelfuse Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
