STMicroelectronics SMP50-120
- Part No.:
- SMP50-120
- Manufacturer:
- STMicroelectronics
- Category:
- Thyristors
- Package:
- DO-214AC, SMA
- Datasheet:
-
SMP50-120.pdf
- Description:
- THYRISTOR 120V 150A DO-214AC
- Quantity:
- Payment:

- Shipping:

Inventory:3,923
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Product details
Overview
SMP50-120 from STMicroelectronics is a bidirectional Trisil™ thyristor surge protection device designed for telecom line interface circuits. It provides crowbar-type overvoltage clamping with a 120 V stand-off voltage (VRM), 160 V dynamic breakover voltage (VBO), 16 mA minimum holding current (IH), 50 A repetitive peak pulse current (10/1000 µs), and 30 pF capacitance at 50 V - enabling robust lightning and transient suppression in xDSL and T1/E1 line cards.
For engineers reviewing the SMP50-120 datasheet, SMP50-120 pinout, SMP50-120 application, or SMP50-120 equivalent, this device is selected for telecom-grade fail-safe short-circuit protection where low capacitance, high surge current capability, and UL497B/GR-1089 compliance are required in analog/digital subscriber line interfaces.
Technical Context
The SMP50-120 operates as a voltage-triggered bidirectional thyristor that latches into low-impedance conduction upon exceeding its dynamic breakover voltage (160 V), sustaining conduction until current falls below its 16 mA minimum holding current. Its fail-safe short-circuit mode ensures continued protection even after degradation.
Designed specifically for telecom surge immunity, it meets GR-1089 Core (first/second level), ITU-T K20/K21, IEC61000-4-5, and FCC Part 68 lightning surge standards - validated with 10/1000 µs, 10/560 µs, and 1.2/50 µs waveforms - and features UL94 V0 epoxy encapsulation and JEDEC DO-214AC (SMA) package compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Stand-off Voltage (VRM) | 120 V - maximum continuous reverse voltage before triggering; defines operating margin above line voltage in protected telecom circuits. |
| Dynamic Breakover Voltage (VBO) | 160 V - voltage at which device triggers into conduction under fast transients (100 V/µs); sets clamping threshold during surge events. |
| Holding Current (IH) | 16 mA min - minimum current required to maintain on-state; ensures reliable latch-off only when line current drops below safe levels. |
| Repetitive Peak Pulse Current (IPP) | 50 A @ 10/1000 µs - peak surge current handling capacity; supports GR-1089 first-level lightning immunity requirements. |
| Junction Capacitance (C) | 30 pF @ 50 V - low signal-line loading; preserves high-frequency integrity in xDSL and ISDN applications up to ~10 MHz. |
| Leakage Current (IRM) | 2 µA max @ 108 V - minimal standby power loss and noise injection; critical for low-power analog line interfaces. |
| Package | SMA (DO-214AC) - surface-mount JEDEC-standard package with 120 °C/W junction-to-ambient thermal resistance; enables automated assembly and PCB space efficiency. |
Pinout & Package
SMP50-120 is housed in an SMA (DO-214AC) surface-mount package with two terminals: Anode (A) and Cathode (K). The package has a standard cathode band marking and is optimized for telecom PCB layouts requiring low parasitic inductance and thermal dissipation via recommended copper pad area.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Anode (A) | Positive conduction path in forward direction; common terminal for bidirectional operation | Connected to line side of telecom interface; carries surge current into device during positive or negative overvoltage events. |
| Cathode (K) | Negative conduction path in forward direction; common terminal for bidirectional operation | Connected to ground or return path; completes low-impedance crowbar path during triggered conduction to shunt energy safely. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional crowbar protection | Triggers symmetrically on both polarities - eliminates need for back-to-back device pairing in AC-coupled telecom lines. |
| Fail-safe short-circuit mode | Guaranteed low-resistance conduction upon end-of-life degradation - prevents open-circuit failure and maintains circuit protection integrity. |
| UL497B certification (E136224) | Validated for primary-side telecom surge protection per FCC Part 68 - reduces qualification effort for certified equipment designs. |
| Low 30 pF capacitance at 50 V | Minimizes high-frequency insertion loss and crosstalk - preserves signal fidelity in broadband DSL and ISDN data transmission. |
| JEDEC DO-214AC (SMA) package | Industry-standard footprint compatible with automated SMT placement and reflow - ensures supply chain compatibility and manufacturing scalability. |
Applications
| DSL Line Cards | T1/E1 Interface Modules |
|---|---|
Use Scenario: Protection of ADSL/VDSL line drivers and receivers against lightning-induced surges on twisted-pair copper loops. IC Role / Device Role / Timing Role: Bidirectional crowbar device placed between line transformer secondary and codec IC input, clamping transients before they reach sensitive analog front-end circuitry. Use Value: Enables compliance with ITU-T K21 and GR-1089 Core first-level surge immunity (2500 V, 10/1000 µs) without degrading 1–30 MHz signal bandwidth. | Use Scenario: Surge protection for T1/E1 channelized interface cards in central office and enterprise PBX systems. IC Role / Device Role / Timing Role: Primary overvoltage protector on balanced receive/transmit pairs, operating in fail-safe short-circuit mode during multi-kA lightning strikes. Use Value: Supports 50 A (10/1000 µs) repetitive surge rating and UL497B listing - satisfies Telcordia GR-1089 second-level (5 kV) and intra-building (1.5 kV) requirements. |
| ISDN Terminal Equipment | FCC Part 68-Certified Modems |
Use Scenario: Overvoltage protection in BRI (Basic Rate Interface) NT1 devices and ISDN terminal adapters connected to PSTN lines. IC Role / Device Role / Timing Role: Standoff-rated protector (120 V VRM) placed across tip/ring lines upstream of isolation transformer, preventing breakdown during AC ringing (100 V RMS). Use Value: 160 V VBO and 2 µA leakage ensure no false triggering during 100 V AC ringing while maintaining <0.1% line distortion at 20 kHz. | Use Scenario: Primary surge suppressor in FCC Part 68-listed analog modems and fax machines connected to telephone network interfaces. IC Role / Device Role / Timing Role: Fail-safe crowbar element in series with line interface IC, activated only during lightning surges (Type A: 1500 V, 10/160 µs) to divert energy to ground. Use Value: UL497B file E136224 and 12.5 Ω minimum series resistor support Type A/B lightning surge compliance without external fuse coordination. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar telecom surge protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SMTPA120 | Same electrical specs (120 V VRM, 160 V VBO, 50 A IPP), but SMB (DO-214AA) package with lower Rth(j-l) = 20 °C/W vs. SMA's 30 °C/W | Higher thermal performance in high-duty-cycle surge environments; requires larger PCB footprint than SMA | Select when thermal management under repeated surges is critical and board space permits SMB layout. |
| TPA120 | Identical electrical ratings, but DO-15 through-hole package with higher thermal mass and 60 °C/W Rth(j-l) | Preferred for legacy telecom hardware with through-hole assembly; less suitable for high-density SMT designs | Choose for repair, replacement, or cost-sensitive industrial telecom equipment using through-hole manufacturing. |
Compared with SMTPA120 and TPA120, SMP50-120 offers optimal balance of compact SMA footprint, automated assembly compatibility, and sufficient thermal performance for most xDSL and T1/E1 line card applications - making it the default choice for new SMT-based telecom interface designs.
Availability
SMP50-120 is available at Aetrix Electronics and suitable for DSL line cards, T1/E1 interface modules, ISDN terminal equipment, and FCC Part 68-certified modems requiring stable component supply and long-term lifecycle support.
Supply support for SMP50-120 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, power, and analog/mixed-signal technologies with broad manufacturing and R&D infrastructure.
The Trisil™ product line was developed specifically for fail-safe, high-reliability surge protection in telecom infrastructure - targeting GR-1089, ITU-T K-series, and FCC Part 68 compliance in analog/digital line interface applications.
FAQ
What is the fail-safe behavior of SMP50-120 during end-of-life degradation?
SMP50-120 fails short-circuit, maintaining a low-impedance path to ground during overvoltage events even after repeated surge stress. This behavior is inherent to its thyristor structure and is verified per UL497B (file E136224), ensuring continued protection without open-circuit risk in telecom line interfaces.
Can SMP50-120 be used in DC-powered telecom circuits such as -48 V central office systems?
Yes - SMP50-120 is bidirectional and rated for 120 V stand-off, making it suitable for -48 V DC systems where differential surges (e.g., 2500 V GR-1089) appear across tip/ring. Its 16 mA minimum holding current ensures reliable latch-off when line current drops below that threshold during normal operation.
How does the 30 pF capacitance affect high-speed DSL signal integrity?
At 30 pF (measured at 50 V, 1 MHz), SMP50-120 introduces negligible insertion loss below 10 MHz - well within ADSL2+ (up to 2.2 MHz) and VDSL2 (up to 30 MHz) bandwidths. Its low capacitance avoids signal attenuation and echo cancellation errors when placed upstream of line drivers/receivers.
Is SMP50-120 RoHS-compliant and lead-free?
Yes - SMP50-120 is supplied in ST's ECOPACK® package with lead-free second-level interconnect, compliant with RoHS Directive 2011/65/EU. The inner box label and package marking indicate the lead-free status per JEDEC JESD97, and soldering profiles follow JEDEC J-STD-020 moisture sensitivity level (MSL) 1 guidelines.
SMP50-120 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Package/Case:
- DO-214AC, SMA
- Series:
- SMP, TRISIL™
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Voltage - Breakover:
- 160V
- Voltage - Off State:
- 120V
- Voltage - On State:
- -
- Current - Peak Pulse (8/20µs):
- 150 A
- Current - Peak Pulse (10/1000µs):
- 50 A
- Current - Hold (Ih):
- 150 mA
- Number of Elements:
- 1
- Capacitance:
- 30pF
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DO-214AC (SMA)
SMP50-120 FAQ
1.How can I place an order for SMP50-120 through Aetrix?
Please submit a Request for Quotation (RFQ) for SMP50-120 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SMP50-120 reliable?
The price and inventory of SMP50-120 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SMP50-120 is usually 5 days.
3.What payment methods are accepted for SMP50-120?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SMP50-120 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SMP50-120?
SMP50-120 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SMP50-120 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SMP50-120?
For technical support, including SMP50-120 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SMP50-120 requirements.
6.How does Aetrix verify that SMP50-120 is sourced from the original manufacturer or authorized distributors?
All SMP50-120 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SMP50-120 meets industry standards.
7.What is the process for return or replacement of SMP50-120?
All SMP50-120 units undergo pre-shipment inspection (PSI). If there is an issue with SMP50-120, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SMP50-120 part is unused and in its original packaging.
Return procedure for SMP50-120:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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