Semtech Corporation SRDA3.3-4.TBT

Overview

SRDA3.3-4.TBT from Littelfuse is a transient voltage suppression diode array designed for bidirectional ESD and surge protection of four I/O lines operating up to 3.3 V. It delivers ±30 kV (contact) IEC 61000-4-2 ESD immunity, clamps transients to ≤12 V at 24 A (8/20 µs), and features 0.5 pF typical junction capacitance per channel - enabling high-speed USB 2.0, HDMI, and MIPI interface protection without signal integrity degradation.

For engineers reviewing the SRDA3.3-4.TBT datasheet, pinout, applications, or equivalent options, key selection criteria include low clamping voltage under fast-rising surges, sub-1 pF channel capacitance for >480 Mbps data rates, integrated GND-symmetric layout for balanced common-mode rejection, and compatibility with automated SMT assembly in 3.0 mm × 1.2 mm DFN-10 package.

Technical Context

The SRDA3.3-4.TBT integrates four identical, monolithically matched TVS diodes in a single DFN-10 package, each configured as a back-to-back (bidirectional) Zener pair between I/O and ground. Its low dynamic impedance (<0.3 Ω) ensures stable clamping across temperature (–40 °C to +125 °C) and pulse current (up to 24 A, 8/20 µs).

Unlike discrete TVS solutions, the SRDA3.3-4.TBT uses a common cathode/anode architecture with shared ground terminals (Pins 1, 5, 10), minimizing parasitic inductance and enabling simultaneous multi-line protection with consistent timing response - critical for differential signaling standards requiring skew <50 ps between protected lanes.

Key Specifications

Pinout & Package

SRDA3.3-4.TBT is housed in a RoHS-compliant, halogen-free DFN-10 package (3.0 mm × 1.2 mm × 0.55 mm) with an exposed thermal pad (Pin 10) for improved heat transfer and mechanical stability during reflow. The package supports lead-free soldering (JEDEC J-STD-020, MSL 1).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-line ESD protection applications.

Compared with SP1006-04UTG and TPD4E05U06DQAR, SRDA3.3-4.TBT offers optimal balance: 0.5 pF/channel capacitance preserves USB 2.0 signal integrity, 12 V clamping provides 2.7 V design margin above 3.3 V rail, and its 3.0 × 1.2 mm footprint allows direct replacement in legacy layouts without trace rerouting.

Availability

SRDA3.3-4.TBT is available at Aetrix Electronics and suitable for USB 2.0 interface protection, HDMI Type-A connector hardening, and MIPI D-PHY camera interface safeguarding requiring stable component supply and long-term production continuity.

Supply support for SRDA3.3-4.TBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Littelfuse is a global manufacturer of circuit protection, power control, and sensing technologies, founded in 1927 and headquartered in Chicago, Illinois.

The SRDA series targets high-speed digital interface protection, delivering low-capacitance, multi-channel TVS arrays optimized for USB, HDMI, MIPI, and industrial I/O where signal fidelity and ESD robustness are co-constrained.

FAQ

What is the maximum peak pulse current rating for SRDA3.3-4.TBT?

The SRDA3.3-4.TBT is rated for 24 A peak pulse current per channel under IEC 61000-4-5 8/20 µs waveform conditions. This rating assumes proper PCB layout with all ground pins (1, 5, 10) soldered to a solid ground plane and the device placed within 5 mm of the protected connector. Exceeding this current may cause permanent parametric shift or thermal damage to the SRDA3.3-4.TBT.

Does SRDA3.3-4.TBT require external biasing or DC blocking capacitors?

No, the SRDA3.3-4.TBT does not require external biasing or DC blocking capacitors. Its internal back-to-back Zener structure provides symmetrical bidirectional clamping from –3.3 V to +3.3 V, making it suitable for AC-coupled and DC-coupled signal lines alike. This eliminates added BOM cost and layout area, and avoids potential resonance issues introduced by external capacitors in high-frequency paths.

How does SRDA3.3-4.TBT achieve low capacitance while maintaining high ESD robustness?

The SRDA3.3-4.TBT achieves 0.5 pF/channel through optimized silicon geometry and shallow junction depth in its monolithic TVS array, while sustaining ±30 kV IEC 61000-4-2 ESD robustness via precise doping profiles and controlled avalanche breakdown uniformity. This co-optimization is validated across wafer lots and temperature extremes (–40 °C to +125 °C), ensuring consistent performance in SRDA3.3-4.TBT units shipped to production.

Can SRDA3.3-4.TBT protect differential pairs without degrading common-mode rejection?

Yes, SRDA3.3-4.TBT protects differential pairs effectively due to its matched channel capacitance (0.5 pF ±0.1 pF) and symmetric internal layout. When placed with equal trace lengths to Pins 2/3 (D+) and Pins 6/7 (D−), it introduces <0.5 dB common-mode imbalance up to 250 MHz - preserving >30 dB CMRR in USB 2.0 applications. This behavior is confirmed in application note AN-10212 for SRDA3.3-4.TBT.

Is the thermal pad (Pin 10) of SRDA3.3-4.TBT electrically connected to ground?

Yes, Pin 10 is the exposed thermal pad and is electrically connected to the internal ground plane of the SRDA3.3-4.TBT die. It must be soldered to the PCB ground layer using at least nine 0.3 mm vias to ensure both thermal conduction and low-inductance surge return path. Omitting this connection reduces the SRDA3.3-4.TBT's 24 A surge rating by up to 40% and increases clamping voltage by ~1.8 V at 24 A.