STMicroelectronics STBP110ETDJ6F

Overview

STBP110ETDJ6F from STMicroelectronics is an overvoltage protection device featuring an integrated 170 mΩ N-channel MOSFET switch, 28 V input overvoltage lockout (OVLO), 1.2 A continuous current rating, thermal shutdown with 20 °C hysteresis, and soft-start control for inrush current limiting - deployed in smartphone power input stages to safeguard battery charging ICs and system rails from adapter overvoltage faults.

For engineers reviewing the STBP110ETDJ6F datasheet, STBP110ETDJ6F pinout, STBP110ETDJ6F application, or STBP110ETDJ6F equivalent, key selection criteria include OVLO threshold accuracy (28 V ±5%), R_DS(on) at 1 A/25 °C, FLT open-drain timing behavior during OVP recovery, EN logic polarity and pull-down strength, and thermal pad soldering requirements for 125 °C junction temperature compliance.

Technical Context

The STBP110ETDJ6F implements a single-channel, high-side N-channel MOSFET protection switch with internal charge pump enabling gate drive above VIN. It continuously monitors IN voltage against programmable OVLO (28 V) and UVLO (typically 4.1 V) thresholds with hysteresis, and junction temperature against 150 °C shutdown threshold with 20 °C hysteresis.

Operation includes controlled soft-start (t_on ≈ 1.2 ms typ.) to limit capacitive inrush, active-low open-drain FLT signaling of OVP or thermal fault conditions, and active-low EN enabling/disabling with internal 250 kΩ pull-down. Reverse current conduction (OUT→IN) is permitted via the MOSFET body diode unless blocked externally.

Key Specifications

Pinout & Package

STBP110ETDJ6F uses a RoHS-compliant 8-lead TDFN package (2 mm × 2 mm × 0.75 mm) with exposed thermal pad internally connected to GND for enhanced thermal dissipation. The package supports reflow soldering per JEDEC J-STD-020 and requires thermal vias under the pad for reliable 125 °C operation at 1.2 A.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar overvoltage protection applications.

Compared with TUSB544RGET and TPD3S014TDR, STBP110ETDJ6F uniquely integrates a 1.2 A rated MOSFET, thermal shutdown, and dedicated FLT signaling in a 2×2 mm footprint - making it the only drop-in solution for space-constrained, high-current adapter input protection without external support components.

Availability

STBP110ETDJ6F is available at Aetrix Electronics and suitable for smartphone power management, digital camera charging interfaces, and portable media player battery protection requiring stable component supply across extended production lifecycles.

Supply support for STBP110ETDJ6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and sensor solutions for automotive, industrial, and consumer markets.

STBP110ETDJ6F belongs to ST's "Protection & Filtering" product line, engineered specifically for robust, integrated overvoltage defense in portable electronics power inputs - emphasizing small footprint, low R_DS(on), and standards-compliant fault response.

FAQ

What is the recommended input capacitor value and placement for STBP110ETDJ6F?

A minimum 1 µF X5R/X7R ceramic capacitor with low ESR must be placed directly between IN and GND, with trace length under 2 mm. This capacitor provides essential decoupling, suppresses fast transients, and enables the ±8 kV contact ESD rating. Larger values (e.g., 4.7 µF) improve noise immunity but do not affect OVLO timing.

Can STBP110ETDJ6F block reverse current flow from OUT to IN?

No - its N-channel MOSFET topology inherently allows reverse conduction via the body diode. To prevent reverse current (e.g., back-powering from battery to adapter), an external Schottky diode must be placed in series with the OUT pin. This adds ~300 mV forward drop but fully isolates paths.

How does the FLT output behave during EN-driven shutdown?

When EN is driven high, FLT enters high-impedance (Hi-Z) state - neither sourcing nor sinking current. It does not assert fault during intentional disable. FLT only pulls low during actual overvoltage or thermal events while EN is low and VIN is above UVLO.

Is the exposed thermal pad required to be soldered to PCB ground?

Yes - the exposed pad is internally connected to GND and is essential for thermal performance. It must be soldered to a solid copper pour with ≥4 thermal vias (0.3 mm diameter) to inner ground layers. Omitting this reduces θ_JA by 40% and risks thermal shutdown at ≤800 mA continuous load.