STMicroelectronics STBP110GTDJ6F

Overview

STBP110GTDJ6F from STMicroelectronics is an overvoltage protection device featuring an integrated 170 mΩ N-channel MOSFET switch, 28 V input overvoltage lockout (OVLO), 1.2 A continuous current rating, thermal shutdown with 20 °C hysteresis, and soft-start for inrush current control - deployed in smartphone power input stages to safeguard battery charging ICs and system rails from adapter overvoltage faults.

For engineers reviewing the STBP110GTDJ6F datasheet, STBP110GTDJ6F pinout, STBP110GTDJ6F application, or STBP110GTDJ6F equivalent, key selection criteria include OVLO threshold accuracy (25.5 V typ.), FLT open-drain fault reporting timing (toff = 1.2 µs max), EN active-low enable logic with internal 250 kΩ pull-down, and TDFN-8 thermal pad layout compatibility for handheld thermal constraints.

Technical Context

The STBP110GTDJ6F implements a monolithic overvoltage protection architecture using an internal high-voltage N-channel MOSFET controlled by analog comparators monitoring VIN against precision UVLO (4.2 V) and OVLO (25.5 V) thresholds with hysteresis. Its charge pump enables full gate drive for low RDS(on) operation without external bias.

Operation includes three fault responses: immediate MOSFET turn-off on OVLO (toff ≤ 1.2 µs), thermal shutdown at TJ ≥ 150 °C (with 20 °C hysteresis), and UVLO disable below 4.2 V. The FLT output is open-drain and asserted low during OVLO or thermal fault, while remaining Hi-Z during EN-disable or UVLO conditions.

Key Specifications

Pinout & Package

STBP110GTDJ6F is housed in a RoHS-compliant 2 mm × 2 mm × 0.75 mm TDFN-8 package with exposed thermal pad (internally connected to GND). The pad must be soldered to a dedicated GND copper pour for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar overvoltage protection applications.

Compared with STBP110GTDJ6F, TUSB544RGER trades dedicated OVP functionality for signal conditioning capability and lacks thermal fault response, while TPD3S014RTER delivers comparable OVLO but increases system-level complexity and thermal burden due to external FET implementation.

Availability

STBP110GTDJ6F is available at Aetrix Electronics and suitable for smartphone power input protection, digital camera battery charging interfaces, and MP3 player USB port hardening requiring stable component supply across high-volume consumer electronics production.

Supply support for STBP110GTDJ6F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, and microcontroller solutions for automotive, industrial, and consumer markets.

The STBP110 belongs to ST's Overvoltage Protection IC product line, engineered specifically for compact, high-reliability front-end protection in battery-powered portable devices operating from unregulated DC sources.

FAQ

What is the recommended input capacitor value and placement for STBP110GTDJ6F?

A minimum 1 µF low-ESR ceramic capacitor must be placed directly between IN and GND, with leads shorter than 2 mm. This capacitor suppresses fast transients and satisfies ESD protection requirements per IEC 61000-4-2. Larger values (e.g., 10 µF) improve hold-up during brief input dips but do not affect OVLO response time.

Can STBP110GTDJ6F support reverse current flow from OUT to IN?

Yes - its N-channel MOSFET topology allows bidirectional conduction via the intrinsic body diode. When OUT voltage exceeds IN, current flows from OUT to IN until IN rises above UVLO (4.2 V), at which point the MOSFET turns on to reduce forward drop. For unidirectional blocking, add a series Schottky diode at the OUT pin.

How does the FLT pin behave during EN-driven shutdown?

When EN is driven high, FLT enters high-impedance (Hi-Z) state - neither sourcing nor sinking current. It does not assert a fault signal during intentional disable. FLT only pulls low during actual overvoltage or thermal fault events, and remains Hi-Z during UVLO or EN-disable, enabling unambiguous fault diagnosis.

Is the exposed thermal pad electrically connected, and how should it be handled in PCB layout?

Yes - the exposed thermal pad is internally connected to GND. It must be soldered to a dedicated GND copper pour covering ≥80% of pad area, with ≥4 thermal vias (0.3 mm diameter) connecting to inner or bottom-layer GND planes. This achieves θJA ≈ 90 °C/W and prevents thermal shutdown under 1.2 A continuous load.