STMicroelectronics STNRG011

Overview

STNRG011 from STMicroelectronics is a digital combo multi-mode PFC + time-shift LLC resonant half-bridge controller in SO20 package, integrating 800 V startup circuitry, line sensing, and X-cap discharge compliant with IEC 62368-1. It delivers fixed-on-time TM/DCM PFC control with input voltage feed-forward, THD optimization, and frequency limiting, plus burst-mode light-load operation with fast transient response - used in high-efficiency open-frame SMPS for flat-screen TVs and ATX power supplies.

For engineers reviewing the STNRG011 datasheet, STNRG011 pinout, STNRG011 application, or STNRG011 equivalent, this device supports UART-based monitoring, black-box logging, and firmware patching via external EEPROM; its dual SMED architecture enables real-time PFC and LLC timing coordination with <25 ns gate-driver rise/fall times and programmable protection thresholds across both power stages.

Technical Context

The STNRG011 implements two independent State Machine Event Driven (SMED) controllers: one for PFC (driving PFC_GD with 0.7 A source / 0.8 A sink) and one for LLC (driving HVG/LVG with 0.5 A source / 0.75 A sink), each triggered by analog comparator outputs (PFC_ZCD, PFC_CS, LLC_CS, LLC_AUX) and internal timers. Its 8-bit core executes PFC loop calculations using a 16×16 MAC unit and 32-bit accumulator, with ADC sampling scheduled per SMED state for real-time current/voltage feedback.

Line monitoring is performed via an internal 20 MΩ resistor divider on VAC, enabling brown-in/out detection (114 V ±2 V), surge stop at 430 V, and X-cap discharge activation after 50 ms of AC inactivity. The HV startup generator delivers up to 8 mA average charge current to VCC from VAC, with clamped VCC operating range (9.5–19 V) and VCORE regulation (4.75–5.25 V) for analog/digital subsystems.

Key Specifications

Pinout & Package

STNRG011 is housed in a 20-pin SOIC (SO20) package with creepage-enhancing NC pins (pins 4 and 19) for reinforced isolation between high-voltage and signal domains. The layout separates PGND (pin 16) and SGND (pin 15) to minimize noise coupling into analog sensing paths.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital combo PFC+LLC controller applications.

Compared with UCC28070 and NCP1654+NCP13992, STNRG011 integrates HV startup, X-cap discharge, UART telemetry, and unified digital control - reducing component count by ≥30%, enabling IEC 62368-1 compliance out-of-box, and supporting post-deployment firmware updates without hardware change.

Availability

STNRG011 is available at Aetrix Electronics and suitable for flat screen TV SMPS, ATX power supply, and open frame SMPS requiring stable component supply, long-term lifecycle support, and compliance with IEC 62368-1 and ENERGY STAR® 8.0 standards.

Supply support for STNRG011 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog devices for industrial, automotive, and consumer markets.

STNRG011 belongs to ST's STNRG digital power controller product line, engineered specifically for high-efficiency, digitally controlled AC-DC converters targeting energy regulations (CoC Tier 2, DoE Level VI) and safety standards (IEC 62368-1).

FAQ

What is the function of the VAC pin beyond startup?

The VAC pin serves three critical roles beyond HV startup: (1) it hosts an internal 20 MΩ resistor divider for line voltage sensing, enabling brown-in/out detection (114 V ±2 V), surge stop at 430 V, and X-cap discharge activation after 50 ms of AC inactivity; (2) it provides line synchronization signals to the PFC controller for sine-wave-aligned switching; and (3) it feeds the AC monitor peripheral for real-time activity tracking used in adaptive burst-mode and fault recovery.

How does STNRG011 achieve compliance with IEC 62368-1 for X-cap discharge?

STNRG011 complies with IEC 62368-1 Annex G by integrating an 800 V-rated HV DMOS on the VAC pin that automatically activates when AC line disconnection is detected (no activity for ≥50 ms), sinking ≥4 mA to discharge X-class capacitors within mandated time limits. This eliminates need for external discharge circuits, reduces BOM, and ensures reliable discharge even during partial-line faults or plug-pull scenarios.

Can STNRG011 operate without external EEPROM for UART communication?

Yes - UART communication is fully functional without external EEPROM. The TX/RX pins support real-time monitoring, parameter read/write, and black-box logging to external memory. External EEPROM is optional and only required for firmware patch upload or persistent black-box storage; all core control functions, protections, and configuration reside in internal ROM and NVM.

What is the role of the SMED architecture in PFC and LLC timing coordination?

The dual SMED (State Machine Event Driven) architecture executes PFC and LLC control loops independently but synchronously: PFC SMED triggers PFC_GD based on PFC_ZCD and PFC_CS events, while LLC SMED drives HVG/LVG using LLC_CS zero-crossing detection. This decouples timing from CPU execution, ensuring deterministic <1 µs protection response and precise phase alignment between PFC output and LLC input - critical for ZVS across load and line variations.