STMicroelectronics STPCI2HEYC

Overview

STPCI2HEYC from STMicroelectronics is a PC-compatible x86 system-on-chip integrating a 133 MHz 5th-generation x86 core, 64-bit SDRAM UMA controller, VGA/SVGA graphics engine with 135 MHz RAMDAC, PCI 2.1 and ISA bus controllers, EIDE, USB 1.1, TFT display interface, and integrated peripheral logic - designed for thin clients and industrial terminals requiring full PC compatibility in a single die.

For engineers reviewing the STPCI2HEYC datasheet, STPCI2HEYC pinout, STPCI2HEYC application, or STPCI2HEYC equivalent, key selection considerations include its 516-pin PBGA package, 2.5 V core operation, unified memory architecture supporting up to 128 MB SDRAM, dual USB host hubs, and legacy I/O integration (PS/2, 16550 UARTs, IEEE 1284 parallel port) without external northbridge.

Technical Context

The STPCI2HEYC implements a fully static 32-bit x86 processor core with 8 KB unified cache, parallel floating-point unit, and dynamic clock control enabling low-power modes (Doze, Standby, Suspend). It embeds a unified memory architecture where system, graphics, and video frame buffers share the same 64-bit SDRAM interface operating up to 90 MHz.

Its graphics subsystem includes a 90 MHz 64-bit enhanced 2D engine with full BitBLT support, hardware clipping, anti-aliased text rendering, and a dedicated video pipeline with CCIR 601/656 input, chroma/color keying, and RGB↔YUV conversion - all coordinated through a single PCI/ISA/LB interconnect fabric with integrated arbitration.

Key Specifications

Pinout & Package

STPCI2HEYC is housed in a 516-pin Plastic Ball Grid Array (PBGA) package with 1.27 mm pitch, designed for high-density PCB layouts and thermal dissipation via exposed thermal pad. Pin functions are multiplexed across memory, PCI, ISA, TFT, and peripheral interfaces per strap configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar x86 system-on-chip applications.

Compared with AMD Geode GX1 and VIA C3-M + VT8235, STPCI2HEYC uniquely integrates ISA, CCIR video input, and TFT control in one 2.5 V device - making it optimal for cost-sensitive, space-constrained terminal designs requiring full legacy compatibility.

Availability

STPCI2HEYC is available at Aetrix Electronics and suitable for thin client terminals, industrial POS systems, and internet appliances requiring stable component supply and long-lifecycle support for legacy-compatible designs.

Supply support for STPCI2HEYC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, analog ICs, and system-on-chip solutions for automotive, industrial, and consumer markets.

The STPC® Atlas product line was engineered to consolidate PC-compatible functionality - x86 processing, graphics, memory, and legacy I/O - into a single chip for cost-sensitive, low-power terminal applications.

FAQ

Is STPCI2HEYC still in production?

No - STPCI2HEYC is an obsolete product as confirmed by STMicroelectronics' official documentation and distributor listings. It remains available through authorized legacy component channels with full traceability, but no new manufacturing runs are planned. Design reuse is supported via verified second-source alternatives and lifecycle management services.

What boot devices does STPCI2HEYC support?

STPCI2HEYC supports boot from EIDE hard drives or CD-ROMs, flash ROM (including 32 MB banks with boot block shadowing to 0x000F0000), and ISA-based ROM devices. It does not support SPI NOR/NAND or SD card boot natively - those require external controller logic or BIOS extension.

Does STPCI2HEYC support DDR SDRAM?

No - STPCI2HEYC supports only SDR SDRAM with -8, -10, -12, -13, and -15 speed grades, operating up to 90 MHz. DDR SDRAM is not electrically or logically compatible; the memory controller lacks double-data-rate strobing, DLL, or impedance calibration circuitry.

Can STPCI2HEYC drive a 1920×1080 TFT panel?

No - the TFT interface supports maximum resolution of 1024×1024 pixels with 9/12/18-bit parallel interface or 2×9-bit dual-pixel mode. Driving 1920×1080 requires external timing controller or LVDS transmitter; the on-chip PWM brightness control and programmable blanking apply only within its native resolution limits.