STMicroelectronics TD352IDT

Overview

TD352IDT from STMicroelectronics is an advanced high-side/low-side IGBT and power MOSFET gate driver in SO-8 package, featuring 1.7 A sink / 1.3 A source peak output current, active Miller clamp, desaturation detection, adjustable turn-on delay (programmable via external RC), and UVLO protection. It enables robust 1200 V three-phase inverter designs with bootstrap high-side supply.

For engineers reviewing the TD352IDT datasheet, TD352IDT pinout, TD352IDT application, or TD352IDT equivalent, key selection considerations include Miller clamp threshold (2.0 V), desaturation trip point (VH−2 V), turn-on delay accuracy (0.7 × Rd × Cd), and SO-8 thermal resistance (150 °C/W) for motor control and UPS systems.

Technical Context

The TD352 integrates a dedicated active Miller clamp circuit that sinks up to 500 mA at VL+4 V max to suppress gate voltage spikes during IGBT off-state, eliminating need for negative gate drive. Its desaturation protection uses an internal 250 µA current source and external capacitor to set blanking time (e.g., ~0.056 µs/pF at VH=16 V).

Turn-on delay is implemented via a precision timing comparator referenced to 2.5 V threshold and discharge resistor (Rdel = 500 Ω typ), enabling reliable deadtime control in half-bridge configurations. The output stage delivers 1.0 A sink / 0.75 A source minimum across −40°C to +125°C, specified near the IGBT Miller plateau region.

Key Specifications

Pinout & Package

TD352IDT is housed in a standard SO-8 surface-mount package (ECOPACK® compliant), with 1.27 mm pitch, 4.8–5.0 mm body width, and 150 °C/W junction-to-ambient thermal resistance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar IGBT gate driver applications.

Compared with IR2110PbF and UCC27531DR, TD352IDT uniquely integrates Miller clamp, desat detection, and programmable deadtime in SO-8 - reducing BOM count and PCB area for IGBT-based 1200 V inverters requiring functional safety margins.

Availability

TD352IDT is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies (UPS), solar inverters, and EV onboard chargers requiring stable component supply, long lifecycle support, and automotive-grade thermal robustness.

Supply support for TD352IDT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for industrial, automotive, and power applications.

The TD352 belongs to ST's high-voltage gate driver product line, engineered specifically for ruggedized IGBT control in 1200 V inverter systems where Miller immunity, desat protection, and bootstrap compatibility are critical.

FAQ

What is the purpose of the CLAMP pin on TD352IDT?

The CLAMP pin provides active Miller current sinking during IGBT off-state. When gate-emitter voltage falls below 2.0 V, CLAMP establishes a low-impedance path to VL, preventing false turn-on caused by dv/dt-induced Miller current. It operates independently of OUT and does not affect turn-off timing, enabling safe bootstrap high-side drive without negative voltage rails.

How is desaturation protection configured on TD352IDT?

DESAT pin monitors IGBT collector-emitter voltage through a resistor divider. When voltage exceeds VH−2 V, internal comparator triggers fault shutdown. Blanking time is set by external capacitor C_des, using internal 250 µA current source: Tbdes ≈ 0.056 × C_des(pF) µs at VH=16 V. Fault latching requires full power cycle reset.

Can TD352IDT drive both IGBTs and MOSFETs?

Yes - TD352IDT is explicitly designed for both IGBTs and power MOSFETs. Its 1.7 A sink / 1.3 A source output current targets IGBT Miller plateau regions, while its 100 ns rise/fall times and 2.5 V logic thresholds suit standard-level MOSFET gates. The active Miller clamp is especially beneficial for IGBTs but also improves noise immunity for high-dv/dt MOSFET switching.

What is the recommended layout practice for the CD pin?

The CD pin must connect to a clean, low-noise external capacitor (e.g., NP0/C0G ceramic) with minimal trace length and no routing near noisy signals. A series resistor is not used - timing relies solely on internal 500 Ω discharge path and external C_d. Layout should avoid shared return paths with power grounds to prevent jitter in turn-on delay timing.