Texas Instruments TPS2145IPWP
- Part No.:
- TPS2145IPWP
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS2145IPWP.pdf
- Description:
- IC ADJ LDO/DUAL SWITCH 14-HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,662
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Product details
Overview
TPS2145IPWP from Texas Instruments is an integrated dual-channel power-distribution switch with an adjustable 1 V to 3.3 V, 200 mA LDO regulator in a single 14-pin TSSOP-PowerPAD package. It features two 340-mΩ (typical) high-side N-channel MOSFETs, independent thermal/short-circuit protection per channel, and CMOS/TTL-compatible active-low enable inputs. It is designed for USB 2.0 bus-powered hubs and portable electronics requiring compact, sequenced, and fault-protected power delivery.
For engineers reviewing the TPS2145IPWP datasheet, TPS2145IPWP pinout, TPS2145IPWP application, or TPS2145IPWP equivalent, key selection criteria include its dual-switch + adjustable-LDO integration, 2.9–5.5 V input range, 340-mΩ typical RDS(on), independent overcurrent flag outputs (OC1/OC2), and thermal shutdown thresholds at 120°C (per switch) and 155°C (global).
Technical Context
The TPS2145IPWP integrates two independently controlled high-side N-channel MOSFET switches and an adjustable LDO on a shared die. Each switch uses internal current-sense FETs and dedicated thermal sensing to enable per-channel fault isolation - a short on OUT1 triggers OC1 and shuts down only SWIN1, leaving OUT2 operational. The LDO employs an internal 0.8 V reference and external resistor divider (LDO_ADJ) to set output from 1 V to 3.3 V with 0.35 V dropout at 200 mA.
Control logic includes active-low EN1/EN2 (pin 14/pin 13) and active-high LDO_EN (pin 10), all compatible with 3-V/5-V logic. An internal charge pump drives MOSFET gates without external components, ensuring controlled turn-on/turn-off timing (0.1–6 ms typical) and minimizing inrush surges. Undervoltage lockout (2.2–2.85 V threshold) disables both switches when VIN/SWIN1 or SWIN2 drops below specification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 2.9 V to 5.5 V - supports standard USB 2.0 bus power and common Li-ion/Li-poly battery rails. |
| Switch RDS(on) (typ) | 340 mΩ at TJ = 25°C - enables ≤150 mA continuous output per switch with <100 mV conduction loss at 300 mA. |
| LDO output range | 1 V to 3.3 V, adjustable via external resistor divider - allows direct powering of core I/O voltages (e.g., 1.8 V, 2.5 V, 3.3 V) from single input rail. |
| LDO dropout voltage | 0.35 V at 200 mA - permits stable regulation even when input drops to 1.35 V above desired output (e.g., 3.3 V out requires ≥3.65 V in). |
| Overcurrent response delay | 5.5 ms assertion / 10.5 ms deassertion - filters transient inrush (e.g., hot-plug capacitive loads) while reliably detecting sustained faults. |
| Thermal shutdown thresholds | 120°C (per-switch trip), 155°C (global shutdown) - provides staged protection: first isolates faulty channel, then fully disables device if cooling fails. |
| Supply current (typ) | 75 µA - enables low-quiescent-power operation in always-on or battery-backed systems. |
Pinout & Package
TPS2145IPWP is housed in a 14-pin TSSOP package with exposed PowerPAD (PWP) for enhanced thermal dissipation. The PowerPAD must be soldered to PCB ground plane for optimal thermal performance and electrical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OUT1) | Power switch 1 output | High-side switched output capable of 150 mA continuous; connects to load requiring independent enable control. |
| 2 (VIN/SWIN1) | Main input supply | Shared input for LDO and Switch 1; must be ≥2.9 V and supplies internal charge pump and regulator reference. |
| 3 (SWIN2) | Power switch 2 input | Dedicated input for second high-side switch; supports independent sourcing from same or separate rail as VIN/SWIN1. |
| 4 (LDO_OUT) | LDO regulated output | Adjustable 1–3.3 V, 200 mA output; requires ≥4.7 µF output capacitor with 200 mΩ–10 Ω ESR for stability. |
| 5 (OUT2) | Power switch 2 output | Second independently enabled high-side output; identical current rating and protection to OUT1. |
| 6, 9 (NC) | No connection | Unbonded pins; must remain unconnected and unpopulated on PCB layout. |
| 7 (LDO_ADJ) | LDO feedback input | Connects to resistor divider midpoint to program LDO output voltage; internal 0.8 V reference sets VOUT = 0.8 × (1 + R1/R2). |
| 10 (LDO_EN) | LDO enable input | Active-high TTL/CMOS-compatible signal; enables/disables LDO independently of power switches. |
| 13 (EN2) | Switch 2 enable | Active-low logic input controlling SWIN2→OUT2 path; pulled up internally when not driven. |
| 14 (EN1) | Switch 1 enable | Active-low logic input controlling VIN/SWIN1→OUT1 path; enables precise sequencing of dual power domains. |
| 11 (OC2), 12 (OC1) | Open-drain fault flags | Active-low indicators asserted during overcurrent; require external pull-up to monitor fault status per channel. |
| 8 (GND) | Ground reference | Common return for all circuits; must be connected to low-impedance PCB ground plane and tied to PowerPAD. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent high-side switches | Each with 340-mΩ typical RDS(on), 150 mA continuous rating, and per-channel thermal/overcurrent protection - enables fault containment without system-wide reset. |
| Adjustable LDO (1–3.3 V, 200 mA) | Programmable via external resistor divider (LDO_ADJ); 0.35 V dropout ensures regulation under low-input conditions typical in portable systems. |
| Integrated charge pump | Eliminates need for external gate-drive components; delivers controlled 0.1–6 ms turn-on/turn-off timing to suppress inrush and EMI. |
| Transient-filtered overcurrent detection | 5.5 ms assertion delay rejects capacitive inrush spikes while reliably triggering on sustained >200 mA faults - reduces false trips in hot-plug applications. |
| Independent enable inputs (EN1, EN2, LDO_EN) | Supports flexible power sequencing: e.g., enable LDO before switches, or stagger OUT1/OUT2 activation for inrush management. |
| Undervoltage lockout (UVLO) | 2.2–2.85 V threshold with 260 mV hysteresis prevents erratic switching during brown-out or battery sag conditions. |
Applications
| USB 2.0 Bus-Powered Hub | Portable DSP Power Sequencing |
|---|---|
|
Use Scenario: A 4-port USB hub powered solely from the host's 5 V bus, requiring isolated power to each downstream port plus regulated 3.3 V for hub controller logic. IC Role / Device Role / Timing Role: TPS2145IPWP acts as dual-port power switch (OUT1/OUT2) + LDO (LDO_OUT) - enabling independent port enable/disable and clean 3.3 V core supply. Use Value: Saves board space vs. discrete switches + LDO; per-port OC1/OC2 flags allow software-controlled port disable on short circuit without affecting other ports. |
Use Scenario: A portable audio DSP platform needing sequential power-up: core logic (1.8 V) before I/O peripherals (3.3 V), with fault isolation between domains. IC Role / Device Role / Timing Role: TPS2145IPWP provides LDO_OUT (1.8 V) and OUT2 (3.3 V) with independent EN1/EN2/LDO_EN control - enabling precise timing of domain activation. Use Value: Eliminates need for external sequencing IC; adjustable LDO supports multiple core voltages; thermal protection prevents damage during I/O initialization faults. |
| Keyboard/Peripheral Power Management | Zip Drive Power Control |
|
Use Scenario: Low-cost keyboard with backlight LED and USB interface, requiring separate 5 V (USB data) and 3.3 V (MCU) rails from single 5 V input. IC Role / Device Role / Timing Role: TPS2145IPWP uses VIN/SWIN1→LDO_OUT (3.3 V MCU) and SWIN2→OUT2 (5 V backlight driver) - decoupling logic and analog power paths. Use Value: Reduces BOM count by integrating LDO and switch; OC2 flag detects LED string open/short, enabling graceful dimming/failure reporting. |
Use Scenario: Legacy Zip drive interface card requiring 5 V motor power and 3.3 V logic, with overcurrent protection against stalled motor conditions. IC Role / Device Role / Timing Role: TPS2145IPWP delivers OUT1 (5 V motor) and LDO_OUT (3.3 V logic) - using EN1 to gate motor power only during spin-up. Use Value: Prevents system reset during motor stall; 120°C per-switch thermal shutdown isolates motor fault while preserving logic supply. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-switch + LDO power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS2147IDGQ | Fixed 3.3 V LDO (no LDO_ADJ/LDO_EN pins); 10-pin MSOP package; same dual-switch architecture and protection features. | Used where fixed 3.3 V output suffices and board space is constrained - eliminates resistor divider but loses voltage flexibility. | Select TPS2147IDGQ when 3.3 V LDO is sufficient and smaller footprint (MSOP-10) is prioritized over adjustability. |
| TPS2155IPWP | Same TSSOP-14 package and pinout as TPS2145IPWP, but with active-high EN1/EN2 (pins 13/14) instead of active-low; identical LDO functionality. | Required in systems where upstream logic uses active-high enable signals - avoids level-shifting or inverters in control path. | Choose TPS2155IPWP only when existing firmware/hardware expects active-high enables; otherwise TPS2145IPWP offers direct compatibility with standard USB hub logic. |
Compared with TPS2147IDGQ, TPS2145IPWP adds voltage adjustability and LDO enable control at the cost of two extra pins; compared with TPS2155IPWP, it retains active-low enables preferred in USB-compliant designs, simplifying interface with standard hub controllers.
Availability
TPS2145IPWP is available at Aetrix Electronics and suitable for USB hubs, portable DSP systems, and peripheral power segmentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS2145IPWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power solutions.
The TPS2145IPWP belongs to TI's power distribution switch + LDO family, engineered specifically for space-constrained, fault-tolerant USB and portable electronics applications demanding integrated sequencing, protection, and regulation.
FAQ
What is the maximum continuous output current per switch in the TPS2145IPWP?
The TPS2145IPWP supports 150 mA continuous output current per switch (OUT1 and OUT2) under recommended operating conditions. This rating assumes proper PCB thermal design - including soldering the PowerPAD to a ground plane - and ambient temperature ≤85°C. Current limiting activates at 200–400 mA depending on junction temperature, with thermal shutdown engaging at 120°C per switch to protect against sustained overload.
How do I configure the adjustable LDO output voltage on the TPS2145IPWP?
To configure the TPS2145IPWP LDO output, connect an external resistor divider between LDO_OUT (pin 4), LDO_ADJ (pin 7), and GND (pin 8). The output voltage follows VOUT = 0.8 V × (1 + R1/R2), where R2 is typically 200 kΩ to establish ~4 µA divider current. For example, setting R1 = 625 kΩ yields 3.3 V; R1 = 250 kΩ yields 1.8 V. A bypass capacitor (e.g., 6 pF at 1.8 V) across R1 may be needed for stability at lower voltages.
Does the TPS2145IPWP support independent fault reporting for each power switch?
Yes, the TPS2145IPWP provides independent open-drain overcurrent flags: OC1 (pin 12) reports faults on OUT1, and OC2 (pin 11) reports faults on OUT2. Each flag asserts low during overcurrent and remains latched until the fault condition clears. This enables per-channel diagnostics in multi-load systems - for instance, a USB hub can disable only the faulty port while maintaining others active - without requiring additional monitoring circuitry.
What is the purpose of the NC pins (6 and 9) on the TPS2145IPWP?
Pins 6 and 9 on the TPS2145IPWP are No Connection (NC) terminals - they have no internal bond wire or circuit connection. These pins must remain unconnected on the PCB; routing traces to or placing solder paste on them risks mechanical stress or unintended coupling. Their presence accommodates package compatibility across the TPS21xx family (e.g., TPS2147 uses different pin assignments), but they serve no functional role in the TPS2145IPWP itself.
Can the TPS2145IPWP operate with input voltages below 3.3 V?
Yes, the TPS2145IPWP operates from 2.9 V to 5.5 V on both VIN/SWIN1 and SWIN2 inputs. However, LDO regulation requires headroom: for a 3.3 V output, input must exceed 3.65 V (3.3 V + 0.35 V dropout); for 1.8 V output, minimum input is 2.15 V. Below 2.9 V, undervoltage lockout disables both switches. Thus, while the device powers on at 2.9 V, usable LDO output depends on selected VOUT and required dropout margin.
TPS2145IPWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- USB, Peripherals
- Current - Supply:
- 75µA
- Voltage - Supply:
- 2.9V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-HTSSOP
TPS2145IPWP FAQ
1.How can I place an order for TPS2145IPWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS2145IPWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS2145IPWP reliable?
The price and inventory of TPS2145IPWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS2145IPWP is usually 5 days.
3.What payment methods are accepted for TPS2145IPWP?
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4.How is shipping managed for TPS2145IPWP?
TPS2145IPWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS2145IPWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS2145IPWP?
For technical support, including TPS2145IPWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS2145IPWP requirements.
6.How does Aetrix verify that TPS2145IPWP is sourced from the original manufacturer or authorized distributors?
All TPS2145IPWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS2145IPWP meets industry standards.
7.What is the process for return or replacement of TPS2145IPWP?
All TPS2145IPWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS2145IPWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS2145IPWP part is unused and in its original packaging.
Return procedure for TPS2145IPWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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