Texas Instruments TPS40120PWR
- Part No.:
- TPS40120PWR
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS40120PWR.pdf
- Description:
- IC PROG FEEDBK DIVIDER 14-TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,790
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS40120PWR from Texas Instruments is a VRM 10.x-compliant, 6-bit digitally programmable feedback divider IC designed to interface with multiphase controllers (e.g., TPS40090) having a 0.7-V internal reference. It supports 12.5-mV VID voltage steps across a 0.8375–1.600-V output range and features dual no-CPU signaling outputs (open-drain NCPU1 and TTL NCPU2) for safe power-down sequencing in Intel® Pentium® 4/Xeon™ processor power supplies.
For engineers reviewing the TPS40120PWR datasheet, TPS40120PWR pinout, TPS40120PWR application, or TPS40120PWR equivalent, this device is selected for precise core voltage regulation in multiphase CPU VRMs where dynamic VID code interpretation, anti-skew filtering (~500 ns), and controller-agnostic 0.7-V reference compatibility are required.
Technical Context
The TPS40120PWR implements a digitally controlled resistive feedback divider with fixed upper resistor and variable lower resistor determined by 6-bit VID inputs (VID0–VID5). Its BIAS pin accepts the controller's 0.7-V reference to improve tolerance tracking, while FB connects to the controller's error amplifier inverting input.
It provides two synchronized no-CPU outputs: NCPU1 (open-drain, used to discharge soft-start capacitors) and NCPU2 (push-pull TTL, used to disable gate drivers). VID input logic thresholds are specified at 0.3 V (low) and 0.85 V (high), with internal anti-skew filtering ensuring glitch-free transitions during VID code changes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Voltage Range (VID Inputs) | -0.1 V to 5.5 V - Ensures robust interfacing with standard CMOS/TTL VID sources without level-shifting. |
| Output Voltage Range (VREF) | 0.8375 V to 1.600 V in 12.5-mV steps - Matches VRM 10.x specification for Intel Pentium 4/Xeon processors. |
| Supply Voltage (VCC) | 4.3 V to 5.5 V - Compatible with standard 5-V system rails; enables direct connection to TPS40090 BP5 pin. |
| Divider Accuracy | ±0.5% - Tight tolerance ensures minimal deviation from target core voltage under varying load/temperature conditions. |
| FB-to-VOUT Resistance | 7.5 kΩ to 14.5 kΩ - Defines gain-setting network impedance compatible with standard compensation networks. |
| VID Input Filtering | ~500 ns anti-skew time constant - Prevents erroneous voltage transitions during rapid VID code updates. |
| Operating Temperature | -40°C to +85°C - Supports industrial-grade CPU power supply operation in server/desktop thermal environments. |
Pinout & Package
TPS40120PWR is housed in a 14-pin TSSOP (PW) package, 5.0 mm × 4.4 mm footprint, 1.2 mm max height, RoHS-compliant, NIPDAU lead finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VID0–VID5 (Pins 1,2,3,4,5,6) | Digital VID code inputs | Accept 6-bit binary code per VRM 10.x table to set VREF; logic thresholds ensure noise immunity. |
| GND (Pin 7) | Signal ground reference | Common return for internal circuitry and external feedback network; must be low-impedance. |
| VOUT (Pin 8) | Divider output node | Connects to differential amplifier output (e.g., TPS40090 DIFFO); forms upper leg of programmable divider. |
| FB (Pin 9) | Feedback tap point | Connects to controller's error amplifier inverting input and compensation network; defines regulated VREF. |
| BIAS (Pin 10) | Reference voltage input | Accepts 0.7-V controller reference to improve divider accuracy and temperature tracking. |
| NCPU1 (Pin 12) | No-CPU open-drain output | Pulls low when VID = x11111; used to discharge SS capacitor and force controlled output ramp-down. |
| NCPU2 (Pin 13) | No-CPU push-pull output | Drives high/low on no-CPU condition; controls gate drivers to place output in high-impedance state. |
| VCC (Pin 14) | Power supply input | 4.3–5.5 V supply; powers internal logic and output drivers; may be sourced directly from TPS40090 BP5. |
Key Features
| Feature | Design Value |
|---|---|
| VRM 10.x compliance | Fully implements Intel VRM 10.x VID code table (64 codes, 12.5-mV steps) for Pentium 4/Xeon core voltage control. |
| Dual no-CPU signaling | Provides both open-drain (NCPU1) and TTL (NCPU2) outputs to coordinate safe power-down across multiphase stages. |
| Controller-agnostic interface | Works with any 0.7-V reference controller (e.g., TPS40090, TPS40130) via BIAS, FB, and VOUT pins-no proprietary protocol required. |
| Anti-skew VID filtering | Integrated ~500 ns input filtering prevents spurious output voltage transients during VID code transitions. |
| TSSOP-14 packaging | Small-footprint 14-pin TSSOP enables dense VRM layouts; compatible with standard SMT assembly and reflow profiles (MSL-1). |
Applications
| Intel Pentium 4 Desktop VRM | Xeon Server Multiphase PSU |
|---|---|
|
Use Scenario: Regulating core voltage for single-socket Pentium 4 systems with dynamic frequency scaling. IC Role / Device Role / Timing Role: Programmable feedback divider that interprets VID codes from the CPU and sets VREF for the TPS40090 controller. Use Value: Enables precise 12.5-mV step voltage adjustment and smooth VID transitions without external resistor networks or firmware intervention. |
Use Scenario: Four-phase 105-A VRM for dual-socket Xeon servers requiring fast VID response and coordinated shutdown. IC Role / Device Role / Timing Role: Central VID decoder and no-CPU coordinator-driving NCPU1/NCPU2 to synchronize phase disablement. Use Value: Eliminates need for discrete logic or FPGA-based VID decoding; reduces BOM count and layout complexity in high-current designs. |
| VRM10.x Reference Design | Legacy Processor Power Upgrade |
|
Use Scenario: TI reference design (SLUU026) implementing VRM10.x compliance using TPS40090 + TPS40120PWR. IC Role / Device Role / Timing Role: Feedback divider element in validated 4-phase topology; interfaces directly with TPS40090 DIFFO and FB nodes. Use Value: Accelerates design validation by providing production-tested signal routing, compensation, and timing margins. |
Use Scenario: Upgrading older VRM9.x systems to support newer Pentium 4 processors requiring VRM10.x VID behavior. IC Role / Device Role / Timing Role: Drop-in replacement for analog dividers or earlier VID ICs-retains same PCB footprint and control interface. Use Value: Enables backward-compatible board revisions without redesigning feedback network or changing controller firmware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable feedback divider applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS40090 + TPS40120PWR combo | TPS40090 is a multiphase controller; TPS40120PWR is its dedicated companion divider-cannot operate standalone. | Used together in full VRM10.x solutions; TPS40120PWR alone does not replace controller functionality. | Select TPS40120PWR only when pairing with a 0.7-V reference controller like TPS40090 or TPS40130. |
| ISL6522CRZ | Intersil VRM10.x-compliant 6-bit VID divider; identical 12.5-mV step resolution but different pinout and no NCPU outputs. | Lacks NCPU1/NCPU2 signaling-requires external logic for no-CPU coordination in multiphase systems. | Choose ISL6522CRZ only if NCPU functionality is unnecessary and pin compatibility with existing layout is verified. |
Compared with TPS40120PWR, the ISL6522CRZ offers matching VID resolution but omits integrated no-CPU outputs, increasing system-level complexity; the TPS40090 is not a substitute but a required partner controller-TPS40120PWR remains unique in its combined VID decoding and dual no-CPU signaling in a 14-pin TSSOP.
Availability
TPS40120PWR is available at Aetrix Electronics and suitable for Intel Pentium 4/Xeon VRM10.x power supplies, multiphase CPU voltage regulators, and legacy processor power upgrades requiring stable component supply and long-term lifecycle support.
Supply support for TPS40120PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in power supply IC design.
The TPS40120PWR belongs to TI's VRM/EVRD power management product line, engineered specifically to simplify compliant core voltage regulation for Intel microprocessors using digital VID interfaces.
FAQ
What is the primary function of the TPS40120PWR in a CPU power supply?
The TPS40120PWR serves as a VRM 10.x-compliant, 6-bit digitally programmable feedback divider. It interprets VID codes from Intel Pentium 4 or Xeon processors and generates a precise reference voltage (0.8375–1.600 V in 12.5-mV steps) for the controller's error amplifier. The TPS40120PWR does not regulate power itself but enables accurate, dynamic core voltage control when paired with a multiphase controller such as the TPS40090.
Does the TPS40120PWR require an external microcontroller or firmware to operate?
No, the TPS40120PWR operates autonomously using only the 6-bit VID signals (VID0–VID5) from the CPU and a 0.7-V reference voltage applied to its BIAS pin. It contains no programmable memory or firmware-its behavior is fully defined by the VRM 10.x VID code table and internal analog divider architecture. The TPS40120PWR requires no configuration, initialization, or host processor interaction.
How do the NCPU1 and NCPU2 pins function in the TPS40120PWR?
When the VID code is set to "x11111" (OFF state), the TPS40120PWR asserts both NCPU1 and NCPU2. NCPU1 is an open-drain output used to discharge soft-start capacitors and initiate controlled output voltage ramp-down. NCPU2 is a push-pull TTL output that can directly drive gate driver enable/disable inputs to place the power stage in high-impedance mode. These outputs provide hardware-coordinated shutdown without software intervention.
Can the TPS40120PWR be used with controllers other than the TPS40090?
Yes-the TPS40120PWR is designed for interoperability with any multiphase controller featuring a 0.7-V internal reference voltage. It has been validated with the TPS40090 and TPS40130, but its BIAS, FB, and VOUT interface is generic. As long as the controller provides a stable 0.7-V reference and accepts a resistive feedback divider topology, the TPS40120PWR can be integrated without modification.
What is the significance of the anti-skew filtering in the TPS40120PWR VID inputs?
The TPS40120PWR incorporates ~500 ns of internal anti-skew filtering on all VID inputs to prevent metastability and transient glitches during simultaneous bit transitions. This ensures that voltage steps occur cleanly and predictably-even during rapid VID code changes-eliminating risk of undershoot, overshoot, or unstable regulation. The filtering is intrinsic to the TPS40120PWR and requires no external components.
TPS40120PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Multiphase Controller
- Current - Supply:
- 1mA
- Voltage - Supply:
- 4.3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
TPS40120PWR FAQ
1.How can I place an order for TPS40120PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS40120PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS40120PWR reliable?
The price and inventory of TPS40120PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS40120PWR is usually 5 days.
3.What payment methods are accepted for TPS40120PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS40120PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS40120PWR?
TPS40120PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS40120PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS40120PWR?
For technical support, including TPS40120PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS40120PWR requirements.
6.How does Aetrix verify that TPS40120PWR is sourced from the original manufacturer or authorized distributors?
All TPS40120PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS40120PWR meets industry standards.
7.What is the process for return or replacement of TPS40120PWR?
All TPS40120PWR units undergo pre-shipment inspection (PSI). If there is an issue with TPS40120PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS40120PWR part is unused and in its original packaging.
Return procedure for TPS40120PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS40120PWR Tags

-
TPS2511DGNR
Texas Instruments

-
UTC2000/MG
Microchip Technology

-
TUSB320HAIRWBR
Texas Instruments

-
TPS61252DSGR
Texas Instruments

-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments

-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments

-
STUSB1600AQTR
STMicroelectronics

-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments

-
TPS65150PWPR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

