Texas Instruments TPS51604DSGT
- Part No.:
- TPS51604DSGT
- Manufacturer:
- Texas Instruments
- Category:
- Gate Drivers
- Package:
- 8-WFDFN Exposed Pad
- Datasheet:
-
TPS51604DSGT.pdf
- Description:
- IC GATE DRVR HALF-BRIDGE 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:159
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Product details
Overview
TPS51604DSGT from Texas Instruments is a synchronous buck MOSFET driver optimized for high-frequency CPU VCORE power delivery, featuring adaptive dead-time control (0–35 ns rising, 0–25 ns falling), integrated bootstrap switch (12–24 Ω RDS(on)), and dual low-power modes (130 µA operating, 8 µA very-low-power). It drives high-side and low-side N-channel FETs in ultrabook and tablet platforms with 4.5–5.5 V VDD input and –40°C to 105°C operation.
For engineers reviewing the TPS51604DSGT datasheet, TPS51604DSGT pinout, TPS51604DSGT application, or TPS51604DSGT equivalent, this page delivers verified technical context on zero-crossing detection, SKIP-mode DCM/FCCM selection, BST-SW voltage management, and WSON-8 thermal pad layout requirements-critical for CPU core rail stability and light-load efficiency optimization.
Technical Context
The TPS51604DSGT implements adaptive dead-time control to minimize shoot-through risk while reducing body diode conduction loss, using real-time DRVL sensing to trigger DRVH turn-on. Its integrated BST switch replaces external diodes, enabling efficient bootstrap capacitor recharge with 120–240 mV forward voltage and <2 µA reverse leakage at 25 V.
Zero-crossing detection operates via the SW pin with ±2.25 mV offset, enabling automatic transition between discontinuous conduction mode (SKIP = LO) and forced continuous conduction mode (SKIP = HI). Tri-state logic on PWM and SKIP pins supports immediate 100 ns exit from low-power states and 50 µs wake-up from 8 µA standby.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDD Range | 4.5 V to 5.5 V - powers internal logic and gate drivers; requires ≥1 µF ceramic decoupling to GND |
| Driver Output Rise Time | DRVH: 30 ns (20–80%), DRVL: 15 ns - enables >1 MHz switching with minimal overlap loss |
| Dead-Time Control | Rising edge: 0–35 ns, falling edge: 0–25 ns - dynamically adjusted to prevent shoot-through without fixed delay penalty |
| Quiescent Current | 130 µA (PWM tri-state), 8 µA (PWM + SKIP tri-state) - sustains ultra-low power state during system sleep |
| UVLO Threshold | 4.15 V (rising), 3.7 V (falling), 0.2 V hysteresis - ensures clean startup/shutdown of gate drive outputs |
| Bootstrap Switch RDS(on) | 12–24 Ω - lowers conduction loss vs. discrete diode, improves high-side FET VGS stability |
| Operating Temperature | –40°C to 105°C - validated for CPU core rail thermal environments in tablets and ultrabooks |
Pinout & Package
TPS51604DSGT uses an 8-pin WSON (DSG) package with 2.00 mm × 2.00 mm body size and exposed thermal pad tied to GND. The thermally enhanced layout supports high-current gate drive with RθJA = 63.1°C/W and RθJB = 34.3°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BST (Pin 1) | Bootstrap supply input | Provides VDD-referenced power for high-side driver; connects to BST capacitor (≥0.1 µF) between BST and SW |
| PWM (Pin 2) | Gate control input | Tri-state enabled: float disables both drivers; VIH = 2.65 V, VIL = 0.6 V accommodates 3.3 V/5 V controllers |
| SKIP (Pin 3) | Mode selection input | LO enables DCM via zero-crossing detection; HI forces FCCM; tri-state enters 8 µA standby with <50 µs wake-up |
| VDD (Pin 4) | Logic supply input | 5 V nominal input; requires ≥1 µF ceramic bypass to GND; UVLO protects against brownout-induced misfire |
| DRVL (Pin 5) | Low-side gate driver output | Drives N-channel FET source; 15 ns rise time, 10 ns fall time, 0.4–1.6 Ω sink resistance for fast turn-off |
| GND (Pin 6) | Reference ground | Return path for DRVL and internal circuitry; must connect thermal pad to system GND plane with multiple vias |
| SW (Pin 7) | Switch node sense | Zero-crossing detection input and high-side return; also serves as BST capacitor return and ZX comparator reference |
| DRVH (Pin 8) | High-side gate driver output | Drives N-channel FET gate; 30 ns rise time, 8 ns fall time, 4–8 Ω source resistance for robust turn-on |
Key Features
| Feature | Design Value |
|---|---|
| Reduced dead-time drive circuit | Adaptive timing eliminates fixed dead-time penalty while preventing shoot-through across load range |
| Automatic zero crossing detection | ±2.25 mV offset SW-sense enables precise DCM entry/exit, improving light-load efficiency by >5% vs. fixed threshold |
| Multiple low-power modes | 130 µA (PWM tri-state only) and 8 µA (PWM + SKIP tri-state) reduce idle power in tablet suspend states |
| Integrated BST switch drive strength | 12–24 Ω RDS(on) and <2 µA leakage at 25 V enable reliable high-side drive for ultrabook-class 30-V FETs |
| Optimized signal path delays | 40 ns DRVH propagation delay and 35 ns DRVL propagation delay support stable 1 MHz+ CPU core regulation |
Applications
| Ultrabook CPU Core Rail | Tablet High-Frequency SoC |
|---|---|
|
Use Scenario: Power delivery to Intel Core i-series or AMD Ryzen Mobile processors requiring dynamic voltage scaling up to 1 MHz switching. IC Role / Device Role / Timing Role: Synchronous buck gate driver coordinating high-side/low-side FETs under TI controller (e.g., TPS51632) with adaptive dead-time and zero-crossing feedback. Use Value: Enables >90% peak efficiency at 12 A load and maintains >85% efficiency at 100 mA via DCM mode, extending battery life in thin-and-light form factors. |
Use Scenario: Core voltage regulation for ARM-based application processors (e.g., Qualcomm Snapdragon) in fanless tablets with strict thermal limits. IC Role / Device Role / Timing Role: Gate driver managing 30-V NexFET power blocks (e.g., CSD87381) with integrated BST switch and SW-node sensing for ripple-aware control. Use Value: Reduces PCB area by eliminating external bootstrap diode and supports compact 2 mm × 2 mm layout while sustaining 105°C junction temperature. |
| Adapter-Powered Notebook Systems | Battery-NVDC Hybrid Rails |
|
Use Scenario: Dual-input power systems accepting 12 V or 19 V adapter input while regulating CPU core at 1.2 V with tight transient response. IC Role / Device Role / Timing Role: High-bandwidth gate driver interfacing with D-Cap+ controllers to deliver sub-100 ns load-step response using adaptive dead-time and fast tri-state wake-up. Use Value: Achieves <20 mV output ripple at 12 A load and recovers from 6 A step in <5 µs, meeting Intel VR13/VR14 specifications. |
Use Scenario: Seamless transition between battery and adapter input in NVDC (Narrow Voltage DC) architectures powering CPU cores from 5 V or 12 V rails. IC Role / Device Role / Timing Role: Robust gate driver with 4.5–28 V VIN tolerance and UVLO hysteresis (0.2 V) ensuring stable operation during input source handoff. Use Value: Maintains uninterrupted CPU operation during adapter plug/unplug events with no output droop or reset, validated across –40°C to 105°C. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51604DSGR | Same silicon, 3000-unit tape-and-reel vs. 250-unit small reel; identical electrical specs and WSON-8 package | No functional difference; selected for high-volume production vs. prototyping or low-MOQ procurement | Choose TPS51604DSGR for cost-sensitive volume builds; TPS51604DSGT remains optimal for design-in validation and pilot runs. |
| ISL6367IRZ | 6-phase capable, higher current drive (1.5 A peak), but larger QFN-48 package and no integrated BST switch | Targets server VRMs and multi-phase desktop CPUs; lacks SKIP-mode DCM optimization for mobile light-load efficiency | Select ISL6367IRZ only for multi-phase, high-current (>25 A) applications where board space and single-phase simplicity are secondary to phase count. |
Compared with TPS51604DSGT, TPS51604DSGR offers identical performance in volume packaging, while ISL6367IRZ trades mobile-optimized DCM efficiency and compact WSON-8 integration for multi-phase scalability-making TPS51604DSGT the sole choice for space-constrained, battery-sensitive CPU core rails.
Availability
TPS51604DSGT is available at Aetrix Electronics and suitable for ultrabook CPU core rails, tablet SoC power delivery, and adapter/battery hybrid systems requiring stable component supply, consistent thermal performance, and long-term lifecycle support.
Supply support for TPS51604DSGT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs for computing, industrial, and automotive markets.
The TPS51604DSGT belongs to TI's CPU core power driver product line, engineered specifically for high-frequency, high-efficiency synchronous buck regulation in portable computing platforms with aggressive thermal and size constraints.
FAQ
What is the function of the SKIP pin on the TPS51604DSGT?
The SKIP pin on the TPS51604DSGT selects between discontinuous conduction mode (DCM) and forced continuous conduction mode (FCCM): when held low, it enables zero-crossing detection for light-load efficiency; when high, it disables DCM for constant-frequency operation; when tri-stated, it places the device in a very-low-power state drawing just 8 µA. This behavior is confirmed in Section 7.3.3 of the SLUSBA6B datasheet and applies directly to the TPS51604DSGT.
Does the TPS51604DSGT require an external bootstrap diode?
No, the TPS51604DSGT integrates a bootstrap switch with 12–24 Ω RDS(on) and <2 µA reverse leakage at 25 V, eliminating the need for an external diode. This internal switch improves reliability and reduces board area versus discrete solutions. The integrated BST switch is explicitly documented in Sections 7.3.5 and 6.5 of the SLUSBA6B datasheet for the TPS51604DSGT.
What is the recommended VDD bypass capacitor value for the TPS51604DSGT?
A ceramic capacitor of 1 µF or greater is required between VDD and GND for the TPS51604DSGT, as specified in Section 5 (Pin Functions) and Section 8.2.2.1 of the SLUSBA6B datasheet. This value ensures stable 5 V logic supply under high dI/dt gate drive transients and meets the device's UVLO hysteresis and noise immunity requirements.
How does the TPS51604DSGT implement shoot-through protection?
The TPS51604DSGT uses adaptive dead-time control that senses DRVL voltage to dynamically adjust DRVH turn-on timing, ensuring no simultaneous conduction of high-side and low-side FETs. Dead-time is programmable from 0–35 ns (rising) and 0–25 ns (falling), as measured in Section 6.5 of the SLUSBA6B datasheet for the TPS51604DSGT under standard test conditions.
What package type and thermal characteristics does the TPS51604DSGT use?
The TPS51604DSGT uses an 8-pin WSON (DSG) package measuring 2.00 mm × 2.00 mm with an exposed thermal pad. Its thermal metrics include RθJA = 63.1°C/W and RθJB = 34.3°C/W, enabling operation up to 105°C junction temperature. These values are specified in Section 6.4 of the SLUSBA6B datasheet and apply to the exact TPS51604DSGT ordering variant.
TPS51604DSGT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Half-Bridge
- Channel Type:
- Synchronous
- Number of Drivers:
- 2
- Gate Type:
- N-Channel MOSFET
- Voltage - Supply:
- 4.5V ~ 5.5V
- Logic Voltage - VIL, VIH:
- 0.6V, 2.65V
- Current - Peak Output (Source, Sink):
- -
- Input Type:
- Non-Inverting
- High Side Voltage - Max (Bootstrap):
- 34 V
- Rise / Fall Time (Typ):
- 30ns, 8ns
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (2x2)
TPS51604DSGT FAQ
1.How can I place an order for TPS51604DSGT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS51604DSGT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS51604DSGT reliable?
The price and inventory of TPS51604DSGT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS51604DSGT is usually 5 days.
3.What payment methods are accepted for TPS51604DSGT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS51604DSGT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS51604DSGT?
TPS51604DSGT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS51604DSGT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS51604DSGT?
For technical support, including TPS51604DSGT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS51604DSGT requirements.
6.How does Aetrix verify that TPS51604DSGT is sourced from the original manufacturer or authorized distributors?
All TPS51604DSGT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS51604DSGT meets industry standards.
7.What is the process for return or replacement of TPS51604DSGT?
All TPS51604DSGT units undergo pre-shipment inspection (PSI). If there is an issue with TPS51604DSGT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS51604DSGT part is unused and in its original packaging.
Return procedure for TPS51604DSGT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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