Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Power Management - Specialized

Texas Instruments TPS65000RTET

Name: TPS65000RTET
Brand: Texas Instruments
SKU: TPS65000RTET
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TPS65000RTET

Manufacturer:: Texas Instruments

Category:: Power Management - Specialized

Package:: 16-WFQFN Exposed Pad

Datasheet:: TPS65000RTET.pdf

Description:: IC CONV STP-DWN 2.25MHZ DL 16QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:515

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TPS65000RTET from Texas Instruments is a single-chip power management IC integrating a 600-mA step-down converter, two 300-mA low-dropout regulators (LDOs), and spread-spectrum clock generation. It operates from 2.3 V to 6 V input, delivers adjustable DC-DC output (0.6 V to V_INDCDC) and supports independent LDO enable/control. Used in portable point-of-load systems requiring compact, efficient multi-rail power.

For engineers reviewing the TPS65000RTET datasheet, TPS65000RTET pinout, TPS65000RTET application, or TPS65000RTET equivalent, key selection criteria include its 2.25-MHz fixed-frequency PWM/PFM operation, dual independent LDO inputs (VINLDO1/VINLDO2), 16-pin 3 mm × 3 mm WQFN package, and absence of integrated supply voltage supervisor - distinguishing it from TPS65001 variants.

Technical Context

The TPS65000RTET implements a synchronous buck converter with internal high-side/low-side MOSFETs (R_DS(on) = 240 mΩ / 185 mΩ), feedback-controlled via FB_DCDC pin referencing a 0.6-V internal bandgap. Its MODE pin selects between automatic PFM/PWM transition (MODE = low) or forced PWM (MODE = high), optimizing efficiency across light-to-heavy loads.

Each LDO features separate input pins (VINLDO1/VINLDO2), enable signals (EN_LDO1/EN_LDO2), and feedback paths (FB_LDO1/FB_LDO2) for externally adjustable outputs. The device lacks SVS functionality - RST, MR, TRST, and RSTSNS pins are unconnected per datasheet; only TPS65001/TPS650061 include supply voltage supervision.

Key Specifications

Parameter	Value and Actual Design Meaning
DC-DC Output Current	600 mA maximum - supports mid-power processor cores or SoC I/O rails without external current boosting.
Switching Frequency	2.25 MHz typical - enables use of small 2.2-μH inductors and 10-μF output capacitors for space-constrained layouts.
LDO Output Current	300 mA per regulator - sufficient for memory interfaces, sensors, or baseband ICs with moderate quiescent demands.
Input Voltage Range	2.3 V to 6 V for DC-DC; 1.6 V to 6 V for each LDO - accommodates single-cell Li-ion, Li-poly, or dual-cell alkaline/battery-backed systems.
DC-DC Reference Voltage	0.6 V ±1% - sets minimum output at 0.6 V; full adjustability requires external resistor divider on FB_DCDC pin.
Quiescent Current	23–32 μA (typical, no switching) - enables >10-year battery life in always-on standby modes for portable devices.
Thermal Resistance	R_θJA = 44.7°C/W - requires minimal PCB copper area for thermal relief under 370 mW max power dissipation at 25°C ambient.

Pinout & Package

TPS65000RTET is housed in a 16-pin, 3.00 mm × 3.00 mm WQFN package (RTE) with exposed thermal pad. Pin numbering follows top-view orientation; thermal pad must be soldered to PCB ground plane for thermal and electrical integrity.

Pin/Terminal	Circuit Role	Design Meaning
1 EN_LDO1	Digital enable input	Active-high signal controlling LDO1 output; ties directly to system power sequencing logic.
2 EN_LDO2	Digital enable input	Independent active-high control for LDO2; allows staggered rail activation or dynamic power gating.
3 PG	Open-drain status output	Asserts low only when all enabled rails (DC-DC + enabled LDOs) are within regulation; requires external pull-up.
4 PGND	Power ground return	Primary return path for DC-DC switch node and LDO pass FETs; must connect to thermal pad and low-impedance GND plane.
5 SW	Switch node output	Connects directly to inductor; carries high di/dt switching current - requires short, wide trace and local ceramic decoupling.
6 VINDCDC	Main DC-DC input	Supplies buck converter and internal control blocks; must be bypassed with ≥10-μF capacitor near pin.
7 MODE	Operation mode select	High = forced PWM (constant frequency); low = automatic PFM/PWM transition for peak efficiency across load range.
8 EN_DCDC	Digital enable input	Active-high enable for step-down converter; controls startup timing and shutdown current (≤2.2 μA).
9 FB_DCDC	Voltage feedback input	Resistor-divider from VDCDC sets output voltage; 0.1-μA input bias enables high-impedance divider design.
10 AGND	Analog ground reference	Reference for FB pins and internal bandgap; must tie to PGND at single point near IC to minimize noise coupling.
11 FB_LDO1	LDO1 feedback input	Adjusts VLDO1 output via external resistor network; supports 0.73 V to (VINLDO1 – V_DO) range.
12 VLDO1	LDO1 regulated output	Delivers up to 300 mA; dropout voltage ≤370 mV at 250 mA ensures stable operation down to VINLDO1 = 1.97 V for 1.6-V output.
13 VINLDO1	LDO1 input supply	Independent input - can be sourced from DC-DC output, battery, or auxiliary rail; supports 1.6–6 V range.
14 FB_LDO2	LDO2 feedback input	Configures VLDO2 output voltage; identical electrical behavior to FB_LDO1 with same bias and accuracy specs.
15 VLDO2	LDO2 regulated output	Second 300-mA rail; output accuracy ±3.5% over full load/temperature ensures reliable peripheral biasing.
16 VINLDO2	LDO2 input supply	Separate input domain enables flexible sequencing - e.g., VINLDO2 from main battery while VINLDO1 from DC-DC.

Key Features

Feature	Design Value
Spread-spectrum clock generation	Reduces EMI peak emissions by modulating 2.25-MHz switching frequency - eliminates need for external EMI filters in handheld designs.
Independent LDO inputs and enables	Enables true multi-source power architecture: VINLDO1 and VINLDO2 may be tied to different supplies (e.g., battery vs DC-DC), with individual enable timing for safe sequencing.
Automatic PFM/PWM mode transition	Maintains >85% efficiency from 100 μA to 600 mA load without firmware intervention - critical for battery runtime in variable-workload applications.
Power-good monitoring with rail-specific logic	PG pin asserts only when all enabled rails meet regulation - prevents system boot until every active voltage rail is valid, avoiding latent faults.
Low quiescent current in shutdown	0.16–2.2 μA shutdown current extends shelf life and enables ultra-low-power wake-on-event architectures.

Applications

Smartphone Baseband Power	Embedded Processor Core Supply
Use Scenario: Powers application processor I/O banks and modem subsystems in dual-SIM smartphones with tight board space and thermal constraints. IC Role / Device Role / Timing Role: Delivers 1.8-V LDO2 rail for SDIO interface and 1.2-V DC-DC rail for DDR termination, synchronized via shared PG signal. Use Value: Single-chip integration reduces BOM count by 3 discrete regulators and eliminates external compensation components for all rails.	Use Scenario: Supplies ARM Cortex-A series SoCs requiring tightly regulated core (VDD_CORE), memory (VDD_IO), and peripheral (VDD_3P3) rails. IC Role / Device Role / Timing Role: DC-DC generates VDD_CORE (1.1 V), LDO1 supplies VDD_IO (1.8 V), LDO2 powers VDD_3P3 (3.3 V); independent enables allow boot sequence control. Use Value: 2.25-MHz switching enables <1-mm² inductor footprint, reducing total solution size by 35% versus 500-kHz alternatives.
Portable Media Player Audio Codec	Point-of-Load for FPGA I/O Banks
Use Scenario: Provides clean, low-noise bias for stereo DAC/ADC and headphone amplifier in flash-based MP3 players. IC Role / Device Role / Timing Role: LDO2 (2.8 V fixed via FB_LDO2 divider) powers analog audio section; DC-DC (1.2 V) feeds digital core; PG confirms both before audio playback starts. Use Value: PSRR >40 dB at 10 kHz suppresses switching noise from DC-DC, eliminating audible artifacts without additional LC filtering.	Use Scenario: Generates multiple FPGA bank voltages (1.2 V, 1.8 V, 3.3 V) on compact carrier boards for industrial vision modules. IC Role / Device Role / Timing Role: DC-DC supplies 1.2-V bank; LDO1 (1.8 V) and LDO2 (3.3 V) serve other banks; independent VINLDOx pins isolate noise between banks. Use Value: Dual LDO inputs prevent cross-rail noise coupling - critical for maintaining signal integrity in high-speed LVDS and MIPI interfaces.

Smartphone Baseband Power

Embedded Processor Core Supply

Use Scenario: Powers application processor I/O banks and modem subsystems in dual-SIM smartphones with tight board space and thermal constraints.

IC Role / Device Role / Timing Role: Delivers 1.8-V LDO2 rail for SDIO interface and 1.2-V DC-DC rail for DDR termination, synchronized via shared PG signal.

Use Value: Single-chip integration reduces BOM count by 3 discrete regulators and eliminates external compensation components for all rails.

Use Scenario: Supplies ARM Cortex-A series SoCs requiring tightly regulated core (VDD_CORE), memory (VDD_IO), and peripheral (VDD_3P3) rails.

IC Role / Device Role / Timing Role: DC-DC generates VDD_CORE (1.1 V), LDO1 supplies VDD_IO (1.8 V), LDO2 powers VDD_3P3 (3.3 V); independent enables allow boot sequence control.

Use Value: 2.25-MHz switching enables <1-mm² inductor footprint, reducing total solution size by 35% versus 500-kHz alternatives.

Portable Media Player Audio Codec

Point-of-Load for FPGA I/O Banks

Use Scenario: Provides clean, low-noise bias for stereo DAC/ADC and headphone amplifier in flash-based MP3 players.

IC Role / Device Role / Timing Role: LDO2 (2.8 V fixed via FB_LDO2 divider) powers analog audio section; DC-DC (1.2 V) feeds digital core; PG confirms both before audio playback starts.

Use Value: PSRR >40 dB at 10 kHz suppresses switching noise from DC-DC, eliminating audible artifacts without additional LC filtering.

Use Scenario: Generates multiple FPGA bank voltages (1.2 V, 1.8 V, 3.3 V) on compact carrier boards for industrial vision modules.

IC Role / Device Role / Timing Role: DC-DC supplies 1.2-V bank; LDO1 (1.8 V) and LDO2 (3.3 V) serve other banks; independent VINLDOx pins isolate noise between banks.

Use Value: Dual LDO inputs prevent cross-rail noise coupling - critical for maintaining signal integrity in high-speed LVDS and MIPI interfaces.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS650001RTET	Fixed 1.2-V DC-DC output; LDO1 = 3.3 V, LDO2 = 1.8 V - no external feedback required for these rails.	Eliminates four external resistors but sacrifices output flexibility; not suitable where adjustable DC-DC or LDO voltages are required.	Select TPS650001RTET only when fixed 1.2/3.3/1.8-V rails match system requirements and layout simplification outweighs configurability needs.
TPS650003RTET	Fixed 1.5-V DC-DC output; LDO1 = 1.8 V, LDO2 = 3.3 V - identical pinout and package, differing only in factory-programmed feedback ratios.	Optimized for systems needing 1.5-V core voltage (e.g., certain DSPs) with complementary 1.8/3.3-V I/O rails; shares same thermal and layout footprint.	Choose TPS650003RTET when 1.5-V DC-DC output aligns with target SoC core voltage and fixed LDO outputs satisfy peripheral requirements.

Compared with TPS65000RTET, TPS650001RTET and TPS650003RTET offer factory-set outputs that reduce component count and layout complexity but eliminate voltage adjustability - making them ideal for high-volume, fixed-rail designs where flexibility is unnecessary.

Availability

TPS65000RTET is available at Aetrix Electronics and suitable for smartphone baseband power, embedded processor core supply, and portable media player audio codec applications requiring stable component supply, long-term manufacturability, and TI-qualified automotive-grade reliability.

Supply support for TPS65000RTET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and personal electronics markets.

The TPS65000 family is designed for portable power management - integrating step-down conversion, dual LDOs, and EMI-reducing spread-spectrum clocking into a single 3-mm × 3-mm WQFN package for space-constrained battery-powered devices.

FAQ

What is the maximum supported input voltage for the DC-DC converter in TPS65000RTET?

The TPS65000RTET DC-DC converter accepts input voltages from 2.3 V to 6 V on the VINDCDC pin. Operation above 6 V violates absolute maximum ratings and risks permanent damage. For systems with higher battery voltages (e.g., 2-cell Li-ion), external pre-regulation is required before connecting to VINDCDC.

Does TPS65000RTET include a supply voltage supervisor (SVS) function?

No, TPS65000RTET does not include a supply voltage supervisor. Pins RST, MR, TRST, and RSTSNS are unconnected internally. SVS functionality is exclusive to TPS65001 and TPS650061 variants. Using TPS65000RTET requires external reset supervision if system-level brownout protection is needed.

How is the DC-DC output voltage set on TPS65000RTET?

The TPS65000RTET DC-DC output voltage is set externally using a resistor divider from VDCDC to AGND, connected to the FB_DCDC pin. The internal 0.6-V reference determines VDCDC = 0.6 V × (1 + R1/R2). Resistor values must ensure FB_DCDC bias current (0.1 μA) introduces <0.5% error - typically achieved with 100-kΩ to 1-MΩ total divider resistance.

What thermal considerations apply to TPS65000RTET in continuous 600-mA operation?

At 600-mA DC-DC load with 3.6-V input and 1.2-V output, TPS65000RTET dissipates ~1.44 W. With R_θJA = 44.7°C/W, junction temperature rise exceeds safe limits without thermal relief. Designers must solder the exposed thermal pad to ≥250 mm² of 2-oz internal GND copper and use thermal vias to inner layers to maintain T_J < 125°C.

Can TPS65000RTET's LDOs be powered from sources independent of the DC-DC converter?

Yes, TPS65000RTET's LDOs accept independent inputs: VINLDO1 and VINLDO2 each support 1.6 V to 6 V and may be sourced from batteries, DC-DC outputs, or auxiliary rails. This enables flexible power tree design - for example, VINLDO1 from a 3.7-V battery and VINLDO2 from the 1.2-V DC-DC output - with no electrical interaction between domains.

TPS65000RTET Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 16-WFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Handheld/Mobile Devices

Current - Supply:: -

Voltage - Supply:: 2.3V ~ 6V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-WQFN (3x3)

TPS65000RTET FAQ

1.How can I place an order for TPS65000RTET through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS65000RTET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS65000RTET reliable?

The price and inventory of TPS65000RTET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65000RTET is usually 5 days.

3.What payment methods are accepted for TPS65000RTET?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65000RTET transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS65000RTET?

TPS65000RTET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS65000RTET order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS65000RTET?

For technical support, including TPS65000RTET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65000RTET requirements.

6.How does Aetrix verify that TPS65000RTET is sourced from the original manufacturer or authorized distributors?

All TPS65000RTET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65000RTET meets industry standards.

7.What is the process for return or replacement of TPS65000RTET?

All TPS65000RTET units undergo pre-shipment inspection (PSI). If there is an issue with TPS65000RTET, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS65000RTET part is unused and in its original packaging.

Return procedure for TPS65000RTET:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…