Texas Instruments TPS65052RSMR

Overview

TPS65052RSMR from Texas Instruments is a 6-channel power management IC integrating two high-efficiency step-down converters (DCDC1: 1 A fixed 3.3 V; DCDC2: 0.6 A selectable 1.0 V or 1.3 V) and four low-input-voltage LDOs (two 400-mA, two 200-mA) for single-cell Li-Ion/Li-Polymer systems. It targets Samsung S3C24xx application processor power rails in portable media players and smartphones.

For engineers reviewing the TPS65052RSMR datasheet, TPS65052RSMR pinout, TPS65052RSMR application, or TPS65052RSMR equivalent, key selection criteria include fixed-output dual-buck architecture, digital LDO voltage selection via DEFLDO pins, 2.25-MHz switching frequency, 32-μA quiescent current in active mode, and QFN-32 (4 mm × 4 mm) package compatibility with space-constrained handheld designs.

Technical Context

The TPS65052RSMR implements two synchronous buck converters operating at 2.25 MHz with 180° out-of-phase switching to reduce input ripple. DCDC1 delivers fixed 3.3 V at up to 1 A; DCDC2 provides 1.0 V or 1.3 V at up to 0.6 A, selected by the DEFDCDC2 pin. Both converters support automatic PFM-to-PWM transition and forced PWM mode via the MODE pin.

Four LDOs are independently enabled: VLDO1/VLDO2 (400 mA each, 1.2–3.3 V output range) and VLDO3/VLDO4 (200 mA each, 1.1–3.3 V), all supporting 1.5–6.5 V input. Digital configuration of LDO output voltages uses four DEFLDO pins (DEFLDO1–DEFLDO4) for 16 preset combinations, eliminating external resistors for standard settings.

Key Specifications

Pinout & Package

TPS65052RSMR uses a 32-pin QFN package (RSM) with exposed thermal pad (PowerPAD™) requiring connection to AGND/PGND for thermal and electrical performance. Pin pitch is 0.4 mm; recommended PCB layout includes thermal vias under the PowerPAD™.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Compared with TPS65051RSMR and TPS65056RSMR, the TPS65052RSMR uniquely combines fixed 3.3-V DCDC1, digital-selectable DCDC2, and digital LDO configuration - minimizing external components for Samsung S3C24xx designs while maintaining full enable/control flexibility.

Availability

TPS65052RSMR is available at Aetrix Electronics and suitable for smartphone baseband power, portable media player system power, and Samsung S3C24xx application processor power requiring stable component supply and long-term industrial availability.

Supply support for TPS65052RSMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with over 50 years of innovation in energy-efficient electronics.

The TPS6505x family was designed specifically for single-cell Li-Ion/Li-Polymer powered portable systems requiring tightly regulated, sequenced, and space-optimized multi-rail power - targeting mobile handsets, PDAs, and media players circa 2007–2012.

FAQ

What is the DCDC1 output voltage of the TPS65052RSMR?

The TPS65052RSMR features a fixed 3.3-V output for DCDC1, delivering up to 1 A without requiring external feedback resistors. This simplifies design for Samsung S3C24xx I/O rail requirements and reduces component count compared to adjustable variants like the TPS65051RSMR. The fixed output is verified in TI's SLVS710A datasheet Section 6.4.

How is the DCDC2 output voltage selected on the TPS65052RSMR?

The TPS65052RSMR uses the DEFDCDC2 pin to select DCDC2 output: logic high sets 1.3 V, logic low sets 1.0 V. This matches the core voltage options for Samsung S3C24xx application processors. Unlike TPS65054RSMR (1.05 V/1.3 V) or TPS65056RSMR (1.0 V/1.2 V/1.3 V), the TPS65052RSMR supports only these two values, as confirmed in the Ordering Information table and Functional Block Diagram.

Does the TPS65052RSMR require external feedback resistors for its LDOs?

No - the TPS65052RSMR uses four digital input pins (DEFLDO1–DEFLDO4) to select from 16 predefined LDO output voltage combinations for VLDO1–VLDO4. This eliminates external resistor dividers required by TPS65051RSMR and TPS65056RSMR. The digital selection is implemented internally and documented in TI's SLVS710A datasheet Section 7.3.

What is the quiescent current of the TPS65052RSMR in active operation?

The TPS65052RSMR draws 32 μA typical total quiescent current into VCC when both DC/DC converters are enabled and operating in PFM mode with no load. This value is measured across –40°C to 85°C and is specified in the Electrical Characteristics table (IQ parameter) of the SLVS710A datasheet. It enables >95% efficiency at light loads typical in portable standby states.

Which package does the TPS65052RSMR use, and what are its thermal characteristics?

The TPS65052RSMR uses the RSM package: a 32-pin QFN (4 mm × 4 mm, 0.4 mm pitch) with an exposed PowerPAD™ thermal pad. Its thermal resistance is RθJA = 58 K/W on a standard board, enabling 0.95 W power dissipation at 70°C ambient. TI recommends soldering the PowerPAD™ to a large copper area with ≥6 thermal vias for optimal performance, per the Package Mechanical Drawing.