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Texas Instruments TPS65052RSMT

Part No.:
TPS65052RSMT
Manufacturer:
Texas Instruments
Category:
Power Management - Specialized
Package:
32-VFQFN Exposed Pad
Datasheet:
AetrixTPS65052RSMT.pdf
Description:
IC PWR MGMT 6CH W/4 LDO 32VQFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:3,124

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Product details

Overview

TPS65052RSMT from Texas Instruments is a 6-channel power-management IC integrating two step-down DC-DC converters (DCDC1 = 1 A at 3.3 V, DCDC2 = 600 mA at 1 V / 1.3 V) and four low-input-voltage LDOs (two 400-mA, two 200-mA) for single-cell Li-Ion/Li-Polymer systems. It supports digital voltage selection via DEF pins, 2.25-MHz fixed-frequency operation, and power-save mode for high efficiency across load ranges - deployed in OMAP™ and S3C24xx application processor power supplies.

For engineers reviewing the TPS65052RSMT datasheet, TPS65052RSMT pinout, TPS65052RSMT application, or TPS65052RSMT equivalent, key selection criteria include its fixed-output DCDC1/DCDC2 configuration, dual enable-controlled LDO banks, 32-pin VQFN package with thermal pad, and compatibility with battery-powered portable media and smartphone baseband subsystems.

Technical Context

The TPS65052RSMT implements two synchronous buck converters operating out-of-phase at 2.25 MHz to reduce input ripple, with DCDC1 optimized for I/O rail (3.3 V, 1 A) and DCDC2 for core voltage (1 V or 1.3 V, 600 mA) selected by DEFDCDC2 logic level. Each converter features 100% duty-cycle capability, ±1% output accuracy in PWM mode, and integrated P/N-channel MOSFETs with rDS(on) ≤630 mΩ (P-ch) and ≤450 mΩ (N-ch).

Four LDOs are digitally configurable via DEFLDO1–DEFLDO4 inputs: LDO1/LDO2 deliver 400 mA each with 280–400 mV dropout at full load; LDO3/LDO4 supply 200 mA each with 280 mV dropout and 70 dB PSRR at 10 kHz. All LDOs accept 1.5–6.5 V input and support independent enable control, reset generation, and push-button ON/OFF sequencing via PB_IN/PB_OUT.

Key Specifications

Parameter Value and Actual Design Meaning
DCDC1 Output Fixed 3.3 V, 1 A - powers system I/O rails without external feedback components.
DCDC2 Output Selectable 1.0 V or 1.3 V (via DEFDCDC2), 600 mA - targets processor core voltage with minimal external logic.
LDO1/LDO2 Current 400 mA each, 280–400 mV dropout - supports noise-sensitive analog/peripheral rails with high PSRR.
LDO3/LDO4 Current 200 mA each, 280 mV dropout, 70 dB PSRR @ 10 kHz - ideal for low-noise sensor or RF bias supplies.
Switching Frequency 2.25 MHz (±10%) - enables compact 2.2 μH inductors and 10–22 μF ceramic output capacitors.
Quiescent Current 32–40 μA (both DC-DCs active, no LDOs enabled) - extends battery life in standby states.
Package 32-pin VQFN (4.0 mm × 4.0 mm, 0.5 mm pitch) with exposed thermal pad - requires PCB thermal vias for 125°C junction operation.

Pinout & Package

TPS65052RSMT uses a 32-pin VQFN package (RSM) with 4.0 mm × 4.0 mm body and exposed thermal pad soldered to PCB ground for thermal management. Pin numbering follows top-view layout with pin 1 at top-left corner.

Pin/Terminal Circuit Role Design Meaning
VCC Power supply for internal circuitry Must tie to same rail as VINDCDC1/2; powers digital/analog blocks and LDO references.
EN_DCDC1 Enable input for DCDC1 Active-high logic; controls startup/shutdown of 3.3-V I/O converter independently.
MODE PFM/PWM mode select Low = power-save (PFM); high = forced PWM - sets tradeoff between light-load efficiency and output ripple.
DEFDCDC2 DCDC2 output voltage select High = 1.3 V, Low = 1.0 V - configures core voltage without resistor dividers.
EN_LDO1–EN_LDO4 Individual LDO enable inputs Active-high logic per LDO; enables precise power-rail sequencing in multi-rail systems.
VLDO1–VLDO4 LDO output terminals Deliver regulated 400-mA (LDO1/LDO2) or 200-mA (LDO3/LDO4) outputs with defined dropout and PSRR.
PGND1/PGND2 Power ground returns Separate ground paths for each DC-DC stage minimize coupling between I/O and core power domains.
FB_DCDC1 DCDC1 feedback input Not used in TPS65052RSMT (fixed 3.3 V); left unconnected or tied to AGND per TI design guidelines.

Key Features

Feature Design Value
Dual fixed-output DC-DC converters Eliminates external feedback resistors for DCDC1 (3.3 V) and DCDC2 (1.0/1.3 V), reducing BOM count and layout area.
Digital LDO voltage configuration Four DEFLDO pins set default LDO1–LDO4 outputs without trimming resistors - simplifies factory programming and variant management.
Independent enable control per rail 11 dedicated EN pins (DCDC1/DCDC2 + LDO1–LDO4) allow custom power-up/down sequencing for SoC compliance.
Integrated push-button interface PB_IN/PB_OUT pins implement hardware-based ON/OFF control with 32-ms debounce - replaces external microcontroller GPIO handling.
Reset generation with threshold monitoring THRESHOLD and HYSTERESIS pins enable undervoltage detection with 100-ms delay - provides clean system reset during brownout.

Applications

Smartphone Baseband Power OMAP™ Application Processor Supply

Use Scenario: Powers ARM-based baseband ICs requiring tightly regulated 3.3-V I/O, 1.3-V core, and auxiliary 1.8-V/2.8-V rails from a single Li-Po cell.

IC Role / Device Role / Timing Role: Central PMIC delivering six synchronized, sequenced power rails with dynamic voltage scaling support via DEF pins.

Use Value: Reduces discrete regulator count by 5+ devices; enables fast wake/sleep transitions using independent EN pins and low-quiescent-current PFM mode.

Use Scenario: Supplies TI OMAP-L138 or OMAP-3530 processors with 3.3-V peripheral, 1.2-V core, and 1.8-V memory interfaces in portable industrial HMIs.

IC Role / Device Role / Timing Role: Single-chip power solution managing DC-DC conversion, LDO regulation, reset assertion, and push-button control.

Use Value: Eliminates need for external reset supervisor and sequencing logic; thermal pad ensures reliable operation at 85°C ambient in sealed enclosures.

Samsung S3C24xx System Power Portable Media Player Subsystem

Use Scenario: Provides 3.3-V I/O, 1.3-V core, and dual 2.8-V/1.8-V LDO rails for Samsung S3C2410/S3C2440 application processors in handheld terminals.

IC Role / Device Role / Timing Role: Integrated power manager with fixed DCDC outputs and programmable LDO defaults matching S3C24xx reference designs.

Use Value: Matches TI's recommended schematic for S3C24xx; DEF pin mapping aligns with standard boot-time voltage configurations.

Use Scenario: Powers audio codec, LCD driver, and NAND flash controller in MP3 players with battery life >10 hours.

IC Role / Device Role / Timing Role: High-efficiency PMIC minimizing idle current draw while maintaining low-noise LDO outputs for analog audio stages.

Use Value: 32–40 μA quiescent current in deep-sleep mode extends runtime; 70 dB PSRR on LDO3/LDO4 suppresses switching noise in headphone amplifiers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar power-management IC applications.

Alternative Part Technical Difference Application Difference Selection Advice
TPS65056RSMT Same 32-pin VQFN package; DCDC1 fixed at 3.3 V (1 A), DCDC2 selectable 1.0/1.3 V (600 mA); LDO voltages externally adjustable via FB pins. Requires external resistor dividers for LDO outputs - less suitable for fixed-voltage production but more flexible for prototyping. Choose TPS65056RSMT when LDO output voltages must be tuned post-design; TPS65052RSMT is preferred for volume production with known, stable LDO requirements.
TPS65051RSMT Same package; both DC-DC converters externally adjustable (DCDC1 = 1 A, DCDC2 = 600 mA); LDO voltages also externally adjustable. Needs full resistor-divider networks for all DC-DC and LDO outputs - increases component count and layout complexity. Select TPS65051RSMT only if variable output voltages are required across multiple product variants; TPS65052RSMT reduces cost and footprint where fixed rails suffice.

Compared with TPS65056RSMT and TPS65051RSMT, the TPS65052RSMT offers lowest BOM count and smallest PCB area for fixed-rail applications, trading configurability for integration density and ease of qualification - critical for cost-sensitive consumer electronics.

Availability

TPS65052RSMT is available at Aetrix Electronics and suitable for smartphone baseband power, OMAP™ application processor supply, and portable media player subsystems requiring stable component supply and long-term lifecycle support.

Supply support for TPS65052RSMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 90 years of innovation in energy-efficient electronics.

The TPS6505x family was designed specifically for single-cell Li-Ion/Li-Polymer portable systems needing compact, highly integrated power solutions - targeting smartphones, PDAs, and application-processor-based embedded devices.

FAQ

What is the DCDC1 output voltage and current capability of the TPS65052RSMT?

The TPS65052RSMT has a fixed 3.3-V output for DCDC1 with up to 1 A continuous current. This rail is intended for system I/O voltage and does not require external feedback components. The device achieves ±1% output accuracy in PWM mode and supports 100% duty cycle for ultra-low dropout operation when input voltage approaches 3.3 V.

How does the DEFDCDC2 pin configure the TPS65052RSMT DCDC2 output?

The DEFDCDC2 pin on the TPS65052RSMT selects between two fixed DCDC2 output voltages: logic high sets 1.3 V, logic low sets 1.0 V. This digital selection eliminates external resistor dividers and simplifies board layout. The pin is sampled at power-up and remains latched until reset or power cycle.

Can the TPS65052RSMT support independent power-rail sequencing?

Yes, the TPS65052RSMT supports full independent sequencing via 11 dedicated enable inputs: EN_DCDC1, EN_DCDC2, and EN_LDO1 through EN_LDO4. Each rail can be activated or disabled under external microcontroller or FPGA control, enabling precise timing alignment with processor boot requirements and power-state transitions.

What is the thermal management requirement for the TPS65052RSMT in continuous operation?

The TPS65052RSMT uses a 32-pin VQFN package with an exposed thermal pad that must be soldered to a PCB ground plane with ≥6 thermal vias (0.3-mm diameter, spaced ≤1 mm apart). With proper layout, it sustains 125°C junction temperature at 85°C ambient, supported by RθJB = 8°C/W and RθJC(bot) = 2.5°C/W thermal metrics.

Is the TPS65052RSMT still in active production or obsolete?

The TPS65052RSMT is marked as obsolete by Texas Instruments per the SLVS710C datasheet revision history. However, Aetrix Electronics maintains legacy inventory and offers extended supply support, including obsolescence mitigation planning, cross-reference assistance, and last-time-buy coordination for ongoing production programs.

TPS65052RSMT Specifications

Product attributes
Attribute value
Manufacturer:
Texas Instruments
Series:
-
Package/Case:
32-VFQFN Exposed Pad
Packaging:
Tape & Reel (TR)
Product Status:
Obsolete
Applications:
Mobile/OMAP™
Current - Supply:
1.25mA
Voltage - Supply:
1.5V ~ 6V
Operating Temperature:
-40°C ~ 85°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
32-VQFN (4x4)

TPS65052RSMT FAQ

1.How can I place an order for TPS65052RSMT through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS65052RSMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS65052RSMT reliable?

The price and inventory of TPS65052RSMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65052RSMT is usually 5 days.

3.What payment methods are accepted for TPS65052RSMT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65052RSMT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS65052RSMT?

TPS65052RSMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS65052RSMT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS65052RSMT?

For technical support, including TPS65052RSMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65052RSMT requirements.

6.How does Aetrix verify that TPS65052RSMT is sourced from the original manufacturer or authorized distributors?

All TPS65052RSMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65052RSMT meets industry standards.

7.What is the process for return or replacement of TPS65052RSMT?

All TPS65052RSMT units undergo pre-shipment inspection (PSI). If there is an issue with TPS65052RSMT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS65052RSMT part is unused and in its original packaging.

Return procedure for TPS65052RSMT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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