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Texas Instruments TPS65054RSMR
- Part No.:
- TPS65054RSMR
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
TPS65054RSMR.pdf
- Description:
- IC PWR MGMT 6CH W/4 LDO 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,236
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Product details
Overview
TPS65054RSMR from Texas Instruments is a 6-channel power-management IC integrating two 600-mA step-down converters (DCDC1 for I/O, DCDC2 for core) and four low-input-voltage LDOs (two 400-mA and two 200-mA), designed for single-cell Li-Ion/Li-Polymer systems in portable processors. It supports digital voltage selection for DCDC2 (1.05 V / 1.3 V) and all four LDOs, operates at 2.25 MHz fixed frequency, and features power-save mode with 32-μA quiescent current for both converters.
For engineers reviewing the TPS65054RSMR datasheet, TPS65054RSMR pinout, TPS65054RSMR application, or TPS65054RSMR equivalent, key selection considerations include dual-buck output current capability, programmable LDO default voltages via DEFLDO[1–4], MODE pin-controlled PFM/PWM operation, and 32-pin VQFN (4 mm × 4 mm) thermal-pad package compatibility with OMAP™ and Samsung S3C24xx application processor power trees.
Technical Context
The TPS65054RSMR implements two synchronous buck converters with integrated high-side/low-side MOSFETs (rDS(on) ≤630 mΩ P-ch, ≤450 mΩ N-ch), 180° out-of-phase switching to reduce input ripple, and internal 600-mV reference for externally adjustable outputs. Its LDO section uses PMOS pass devices with 70 dB PSRR at 10 kHz and dropout as low as 280 mV at full load.
Control logic includes independent enable pins per rail (EN_DCDC1/2, EN_LDO1–4), digital voltage select inputs (DEFDCDC2, DEFLDO1–4), and MODE pin forcing PWM or power-save (PFM) mode. The device integrates a 32-ms debounce flip-flop for push-button interface and supports sequencing via external enable coordination.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DCDC Output Current | 2 × 600 mA - sufficient for I/O and core rails of mid-tier application processors without external current boosting |
| Switching Frequency | 2.25 MHz ±10% - enables use of compact 2.2-μH inductors and 10–22-μF ceramic output capacitors |
| LDO Output Current | 2 × 400 mA + 2 × 200 mA - supports mixed-signal peripherals, memory interfaces, and auxiliary logic with high PSRR |
| Input Voltage Range | VINDCDC1/2: 2.5–6 V; VINLDOx: 1.5–6.5 V - compatible with direct battery input or pre-regulated supply from DCDC outputs |
| Quiescent Current | 32 μA (both DCDCs active, no LDOs enabled) - extends battery life in standby states of portable devices |
| Output Accuracy | ±1% in PWM mode - ensures stable core/I/O voltage margins under dynamic load for ARM-based SoCs |
| Package | 32-pin VQFN (4.0 mm × 4.0 mm, 0.5-mm pitch) with exposed thermal pad - optimized for thermal performance in space-constrained handheld PCBs |
Pinout & Package
TPS65054RSMR is housed in a 32-pin VQFN package (4.0 mm × 4.0 mm) with an exposed thermal pad soldered to PCB ground for enhanced thermal dissipation. Pin numbering follows standard top-view orientation with Pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply for internal analog/digital circuitry | Must be tied to same node as VINDCDC1/2; powers control logic, references, and LDO bias networks |
| EN_DCDC1 / EN_DCDC2 | Active-high enable inputs | Enable/disable DCDC1 (I/O) and DCDC2 (core) independently for power sequencing and dynamic rail control |
| MODE | PFM/PWM mode select | Low = automatic power-save (PFM at light load); High = forced fixed-frequency PWM for low-noise operation |
| DEFDCDC2 | DCDC2 output voltage select | High = 1.05 V, Low = 1.3 V - sets core voltage for specific processor operating points |
| DEFLDO1–DEFLDO4 | LDO1–LDO4 default voltage select | 4-bit binary input (LSB–MSB) configuring initial LDO output voltages before software reprogramming |
| EN_LDO1–EN_LDO4 | Active-high LDO enable inputs | Per-rail control allows dynamic activation of 400-mA (LDO1/LDO2) and 200-mA (LDO3/LDO4) regulators |
| FB_DCDC1 | DCDC1 feedback input | Connects to external resistor divider to set VDCDC1 between 0.6 V and VINDCDC1/2 |
| L1 / L2 | DCDC1/DCDC2 switch node outputs | Drive external inductors; require low-ESR ceramic capacitors and proper layout for EMI suppression |
| PGND1 / PGND2 | Power ground returns | Separate grounds minimize coupling between buck converter switching loops and improve stability |
| VINLDO1–VINLDO3/4 | LDO input voltage supplies | Accept 1.5–6.5 V; may be fed from battery or from DCDC outputs for cascaded regulation |
| VLDO1–VLDO4 | LDO regulated output terminals | Deliver 400-mA (VLDO1/VLDO2) or 200-mA (VLDO3/VLDO4) with 70 dB PSRR at 10 kHz |
| BP | Bypass capacitor connection | Stabilizes internal reference; requires 1-μF ceramic capacitor to AGND |
| AGND | Analog ground reference | Must be connected to PGND and thermal pad; serves as reference for FB and threshold circuits |
Key Features
| Feature | Design Value |
|---|---|
| 2.25-MHz fixed-frequency operation | Enables miniaturized filter components (2.2-μH inductors, 10–22-μF ceramics), reducing solution footprint by >40% vs lower-frequency PMICs |
| 180° out-of-phase DCDC switching | Halves input ripple current magnitude and reduces required input capacitance, easing EMI compliance in dense layouts |
| Digital voltage selection (DEF pins) | Hardware-configurable default voltages eliminate boot-time software dependency for critical rails like core and I/O |
| 32-μA quiescent current (dual DCDC) | Extends system standby time in always-on applications such as cellular IoT nodes and wearable sensors |
| 70 dB PSRR at 10 kHz (LDOs) | Suppresses switching noise from DCDC outputs when powering noise-sensitive analog/RF blocks or ADC references |
| Independent per-rail enable control | Supports precise power-up/down sequencing required by OMAP™, S3C24xx, and other application processors |
Applications
| Smartphone Baseband Power | OMAP™ Application Processor Supply |
|---|---|
Use Scenario: Dual-rail power delivery for baseband SoC requiring separate 1.3-V core and 3.3-V I/O supplies, plus auxiliary 1.8-V and 2.8-V rails for RF transceivers and memory. IC Role / Device Role / Timing Role: Primary PMIC managing all voltage domains, sequencing, and dynamic voltage scaling under processor command. Use Value: Eliminates need for discrete DCDCs and LDOs, reducing BOM count by 6+ components while maintaining ±1% output accuracy across temperature. |
Use Scenario: Powering TI OMAP-L138 or OMAP3530 with configurable core voltage (1.05 V/1.3 V), I/O voltage (3.3 V), and peripheral rails (1.8 V, 2.8 V). IC Role / Device Role / Timing Role: Integrated power controller providing hardware-programmable defaults and software-controllable enable/sequencing via GPIOs. Use Value: Enables fast boot from cold start using DEF pin settings, then transitions to dynamic DVFS during runtime without external intervention. |
| Samsung S3C24xx System Power | Portable Media Player Power Tree |
Use Scenario: Supporting Samsung S3C2410/S3C2440 application processors with 1.3-V core, 3.3-V I/O, 1.8-V USB PHY, and 2.8-V LCD interface. IC Role / Device Role / Timing Role: Centralized power manager handling reset generation, push-button ON/OFF control, and rail enable coordination. Use Value: Integrates PB_IN/PB_OUT debounce logic and RESET delay (100 ms), removing need for external timing RC networks and microcontroller polling. |
Use Scenario: Powering audio codec, NAND flash, SD card interface, and color LCD in portable media players with battery input ranging from 4.2 V (full) to 3.0 V (low). IC Role / Device Role / Timing Role: Efficient multi-rail regulator delivering stable outputs across wide input range using PFM mode at light loads. Use Value: Achieves >90% efficiency at 10-mA loads via automatic PFM entry, extending playback time by up to 22% versus fixed-PWM alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65050RSMR | Fixed LDO output voltages per Table 1; DCDC1/DCDC2 externally adjustable; no digital voltage select on DEF pins | Requires external resistors to set all LDO outputs; less flexible for firmware-driven voltage scaling | Select when LDO voltages are static and board space permits external programming resistors |
| TPS65056RSMR | DCDC1 fixed at 3.3 V; DCDC2 selectable between 1.0 V and 1.3 V; LDO voltages externally adjustable | Optimized for systems needing fixed I/O voltage but variable core voltage; higher DCDC1 current (1 A) | Select when I/O rail is invariant and core rail must scale, especially with higher-current SoCs |
Compared with TPS65050RSMR and TPS65056RSMR, the TPS65054RSMR uniquely combines externally adjustable DCDC1, digitally selectable DCDC2 (1.05 V/1.3 V), and fully programmable LDO defaults-making it optimal for designs requiring hardware-configurable core voltage without sacrificing I/O flexibility.
Availability
TPS65054RSMR is available at Aetrix Electronics and suitable for smartphone baseband power, OMAP™ application processor supply, Samsung S3C24xx system power, portable media player power trees, and wearable sensor node power management requiring stable component supply across extended production lifecycles.
Supply support for TPS65054RSMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with decades of leadership in high-efficiency DC-DC conversion and integrated PMIC design.
The TPS6505x product line was engineered specifically for single-cell Li-Ion/Li-Polymer powered portable systems-including smartphones, PDAs, and media players-delivering compact, sequenced, and highly efficient multi-rail power in a thermally robust VQFN package.
FAQ
What is the maximum output current supported by each DC-DC converter in the TPS65054RSMR?
The TPS65054RSMR supports 600 mA per DC-DC converter-DCDC1 for I/O voltage and DCDC2 for core voltage. This rating is validated across the full input range (2.5 V to 6 V) and ambient temperature (–40°C to 85°C), with thermal derating applied above 70°C per the RθJA = 37.3°C/W specification. The TPS65054RSMR does not support higher currents like the 1-A DCDC1 found in TPS65051RSMR or TPS65056RSMR.
How does the MODE pin affect efficiency and noise performance of the TPS65054RSMR?
When the MODE pin is pulled low, the TPS65054RSMR enters power-save mode (PFM), achieving peak efficiency (>95%) at light loads (e.g., <10 mA) but with variable switching frequency and higher output ripple. When MODE is pulled high, it forces fixed-frequency PWM operation at 2.25 MHz, delivering tighter output regulation (±1%), lower ripple, and predictable EMI-ideal for noise-sensitive analog sections. The TPS65054RSMR's 32-μA quiescent current applies only in PFM mode with both DCDCs active and no LDOs enabled.
Can the TPS65054RSMR generate a system reset signal, and how is it configured?
No-the TPS65054RSMR does not integrate a RESET output. Unlike TPS65051RSMR and TPS65056RSMR, which feature an open-drain RESET pin with 100-ms delay, the TPS65054RSMR omits this function. Instead, it provides PB_IN and PB_OUT pins for push-button ON/OFF control with 32-ms debounce. For reset functionality, external supervision ICs or processor-integrated reset controllers must be used alongside the TPS65054RSMR.
What are the valid output voltage options for DCDC2 on the TPS65054RSMR, and how are they selected?
The TPS65054RSMR supports two fixed DCDC2 output voltages: 1.05 V (when DEFDCDC2 = high) and 1.3 V (when DEFDCDC2 = low). These values are factory-trimmed and do not require external feedback resistors. DCDC1 remains externally adjustable via FB_DCDC1 and a resistor divider. This dual-voltage capability enables hardware-selectable core operating points for processors like OMAP-L138 that support multiple performance states.
Does the TPS65054RSMR support independent enable control for all six power rails?
Yes-the TPS65054RSMR provides dedicated active-high enable inputs for both DC-DC converters (EN_DCDC1, EN_DCDC2) and all four LDOs (EN_LDO1 through EN_LDO4), enabling full hardware-based sequencing. Each rail can be turned on/off independently without affecting others, allowing custom power-up order (e.g., LDOs before DCDCs) or dynamic rail gating during low-power modes. This capability is identical across the TPS6505x family and essential for meeting OMAP™ and S3C24xx processor power requirements.
TPS65054RSMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Mobile/OMAP™
- Current - Supply:
- 1.25mA
- Voltage - Supply:
- 1.5V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (4x4)
TPS65054RSMR FAQ
1.How can I place an order for TPS65054RSMR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65054RSMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65054RSMR reliable?
The price and inventory of TPS65054RSMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65054RSMR is usually 5 days.
3.What payment methods are accepted for TPS65054RSMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65054RSMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65054RSMR?
TPS65054RSMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65054RSMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65054RSMR?
For technical support, including TPS65054RSMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65054RSMR requirements.
6.How does Aetrix verify that TPS65054RSMR is sourced from the original manufacturer or authorized distributors?
All TPS65054RSMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65054RSMR meets industry standards.
7.What is the process for return or replacement of TPS65054RSMR?
All TPS65054RSMR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65054RSMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65054RSMR part is unused and in its original packaging.
Return procedure for TPS65054RSMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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