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Texas Instruments TPS65055RSMT
- Part No.:
- TPS65055RSMT
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
TPS65055RSMT.pdf
- Description:
- IC DUAL STP-DN CONV W/LDO 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:250
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Product details
Overview
TPS65055RSMT from Texas Instruments is a highly integrated power management IC (PMIC) for single-cell Li-ion/Li-polymer systems, featuring two 600 mA synchronous step-down converters and four low-input-voltage LDOs - two 400 mA (VLDO1, VLDO2) and two 200 mA (VLDO3, VLDO4). It operates at 2.25 MHz fixed frequency with 180° out-of-phase switching, supports I²C voltage programming, and delivers ±1% DCDC output accuracy in PWM mode. It is used in smartphone baseband processors to supply core (DCDC2) and I/O (DCDC1) rails while powering auxiliary analog/digital subsystems via LDOs.
For engineers reviewing the TPS65055RSMT datasheet, TPS65055RSMT pinout, TPS65055RSMT application, or TPS65055RSMT equivalent, key selection considerations include dual-DCDC efficiency at light/heavy loads, digital LDO voltage selection via DEFLDO1/DEFLDO2 pins, I²C programmability, thermal shutdown at 140°C, and compatibility with small 2.2 µH inductors and 10–22 µF ceramic output capacitors.
Technical Context
The TPS65055RSMT integrates two independent synchronous buck converters sharing a 2.25 MHz oscillator with 180° phase shift to reduce input ripple current and enable smaller input capacitance. Each converter uses voltage-mode control with input-voltage feedforward for fast line/load regulation and includes internal P-channel (630 mΩ typ.) and N-channel (450 mΩ typ.) MOSFETs with 1.0 A forward current limit.
Four LDOs are digitally configurable: VLDO1/VLDO2 (400 mA, 0.8–2.8 V / 1.2–3.0 V) and VLDO3/VLDO4 (200 mA, 0.8–2.8 V / 1.2–3.0 V), set by dual-bit DEFLDO1/DEFLDO2 inputs yielding nine combinations. All LDOs support 1.5–6.5 V input, deliver ≥70 dB PSRR at 10 kHz, and feature internal 350 Ω discharge resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DCDC Output Current | 2 × 600 mA - sufficient to power OMAP™/XScale™ processor core and I/O rails simultaneously |
| Switching Frequency | 2.25 MHz (±10%) - enables use of compact 2.2 µH inductors and reduces EMI filtering burden |
| LDO Output Current | VLDO1/VLDO2: 400 mA; VLDO3/VLDO4: 200 mA - supports RF transceivers, audio codecs, and sensors |
| Output Voltage Accuracy | ±1% in PWM mode - ensures stable core voltage under dynamic load for reliable CPU operation |
| Quiescent Current | 40–55 µA (both DCDCs active, all LDOs off) - extends battery life in standby without compromising wake-up speed |
| Thermal Shutdown | 140°C with 20°C hysteresis - protects against sustained overload or poor PCB thermal design |
| I²C Interface | Standard-mode compatible (100 kHz) - allows runtime voltage scaling and fault monitoring in system firmware |
Pinout & Package
The TPS65055RSMT is housed in a 4.0 mm × 4.0 mm, 32-pin VQFN package (RSM) with 0.4 mm pitch and exposed PowerPAD™ thermally connected to AGND. The package supports high-density portable layouts and requires controlled-impedance routing for SCLK/SDAT and proper thermal vias under the PowerPAD™.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN_DCDC1 / EN_DCDC2 | Enable inputs (active-high) | Independent hardwired control of each buck converter; essential for sequenced power-up in multi-rail systems |
| DEFDCDC2 | DCDC2 output voltage select | Logic-high = 1.0 V, logic-low = 1.2 V - sets default core voltage without I²C interaction |
| DEFLDO1 / DEFLDO2 | LDO output voltage configuration bits | 2-bit code selects one of nine LDO voltage combinations - enables flexible rail assignment across peripherals |
| VDCDC1 / VDCDC2 | Feedback sense inputs | Must connect directly to respective output nodes; no external resistor divider allowed per datasheet |
| SCLK / SDAT | I²C clock/data lines | Open-drain compatible; require external pull-ups - enable dynamic voltage adjustment and status readback |
| RST / DPD / discharge | Open-drain status outputs | RST/DPD signal UVLO events; discharge controls external capacitor discharge - critical for safe power-down |
Key Features
| Feature | Design Value |
|---|---|
| 180° out-of-phase DCDC operation | Reduces RMS input current by ~30%, allowing smaller 22 µF input capacitors instead of 47 µF |
| Power save mode (PFM) | Automatically engages below ~10 mA load, cutting quiescent current to 30–40 µA per converter |
| High PSRR LDOs (70 dB @ 10 kHz) | Suppresses switching noise from DCDCs, enabling clean analog supply for ADCs and RF front-ends |
| Internal 350 Ω discharge resistors | Ensures rapid LDO/DCDC output discharge during shutdown - prevents back-powering of powered-down domains |
| 100% duty-cycle capability | Supports ultra-low dropout operation when VIN approaches VOUT - critical for battery brownout resilience |
Applications
| Smartphone Baseband Power | WLAN/Bluetooth Module Supply |
|---|---|
|
Use Scenario: Powers OMAP™ or similar application processor in dual-SIM smartphones with tight board space and aggressive battery life targets. IC Role / Device Role / Timing Role: Provides tightly regulated 1.2 V core (DCDC2) and 2.1 V I/O (DCDC1) rails; supplies 3.3 V LDO1 for memory interface and 1.8 V LDO2 for camera sensor. Use Value: 95% peak efficiency and 40 µA quiescent current extend talk time; I²C programmability enables adaptive voltage scaling during different usage modes. |
Use Scenario: Supplies 3.3 V WLAN radio and 1.8 V Bluetooth baseband IC in portable hotspot devices. IC Role / Device Role / Timing Role: Delivers low-noise 3.3 V from VLDO1 (400 mA) and 1.8 V from VLDO3 (200 mA); DCDC converters remain active to sustain main SoC rails. Use Value: 70 dB PSRR prevents DCDC switching noise from degrading WLAN EVM; 200 mA LDO3 headroom accommodates Bluetooth transmit burst currents. |
| Digital Camera Sensor Bias | Portable Media Player Audio Codec |
|
Use Scenario: Powers CMOS image sensor requiring precise, low-ripple bias voltages in compact action cameras. IC Role / Device Role / Timing Role: Uses VLDO2 (400 mA) for 2.85 V analog sensor supply and VLDO4 (200 mA) for 1.3 V digital interface; DCDCs supply main SoC and display drivers. Use Value: Internal 350 Ω discharge resistors ensure sensor bias ramps down cleanly between frames, eliminating image artifacts from residual charge. |
Use Scenario: Supplies stereo audio codec (DAC/ADC) and headphone amplifier in flash-based MP3 players. IC Role / Device Role / Timing Role: Delivers 1.2 V LDO3 for digital core and 3.3 V LDO1 for analog section; DCDC converters power NAND controller and LCD backlight driver. Use Value: ±1% DCDC accuracy maintains consistent audio sample clock generation; low 25 mVPP PFM ripple avoids audible switching noise in analog audio path. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management IC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65053RSMT | Omits I²C interface; fixed LDO voltages set only by DEFLDO pins; identical DCDC specs and pinout | Suitable for cost-sensitive designs where runtime voltage reconfiguration is unnecessary | Select when firmware-level rail control is not required and BOM simplification is prioritized |
| TPS65056RSMT | Replaces VLDO3/VLDO4 (200 mA) with second 400 mA LDO pair; same DCDC and package | Better suited for systems needing higher-current auxiliary rails (e.g., dual-camera modules) | Choose when >200 mA is needed on LDO3/LDO4 rails and additional 400 mA capacity justifies part change |
Compared with TPS65055RSMT, the TPS65053RSMT removes I²C programmability but retains identical power delivery capability and footprint, while the TPS65056RSMT upgrades LDO3/LDO4 to 400 mA each - offering higher flexibility for multi-peripheral systems at the cost of reduced LDO voltage combination granularity.
Availability
TPS65055RSMT is available at Aetrix Electronics and suitable for smartphone baseband, WLAN module, digital camera, portable media player, and OMAP™/XScale™ processor applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS65055RSMT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in battery-powered portable systems.
The TPS65055RSMT belongs to TI's portable PMIC product line, designed specifically for single-cell Li-ion systems in smartphones, PDAs, and media players - emphasizing high integration, efficiency across load ranges, and robust sequencing control.
FAQ
What is the maximum input voltage supported by the TPS65055RSMT DCDC converters?
The TPS65055RSMT DCDC converters accept an input voltage range of 2.5 V to 6 V on the VINDCDC1/2 pin. This range accommodates fully charged single-cell Li-ion (up to 4.2 V) and extended-range batteries or adapter inputs. Exceeding 6 V risks permanent damage, as confirmed by the Absolute Maximum Ratings table specifying 7 V as the absolute limit only for brief transient conditions.
Can the TPS65055RSMT operate without an I²C host controller?
Yes, the TPS65055RSMT functions fully without I²C. DCDC output voltages are set by DEFDCDC2 (for DCDC2) and DEFLDO1/DEFLDO2 (for DCDC1 and all LDOs), and all regulators can be enabled/disabled via dedicated EN pins. I²C is optional and used only for dynamic reprogramming - the device defaults to pin-configured voltages at power-up.
What is the purpose of the discharge pin on the TPS65055RSMT?
The discharge pin on the TPS65055RSMT is an open-drain output driven by the threshold comparator. When the THRESHOLD pin voltage falls below 0.8 V, the discharge pin actively pulls low to discharge external capacitors connected to DCDC or LDO outputs. This ensures safe, controlled power-down and prevents back-powering of disabled circuit blocks.
How does the TPS65055RSMT manage efficiency at light loads?
The TPS65055RSMT automatically enters pulse-frequency modulation (PFM) mode at light loads (< ~10 mA), reducing switching frequency and quiescent current to 30–40 µA per DCDC converter. This preserves >85% efficiency down to 100 µA load, significantly extending battery runtime in standby or idle states compared to forced-PWM operation.
What thermal performance can be expected from the TPS65055RSMT in a standard 2-layer PCB layout?
In a standard 2-layer PCB with 4 thermal vias under the PowerPAD™, the TPS65055RSMT exhibits a junction-to-board thermal resistance (RθJB) of 7.8°C/W. At full 600 mA load per DCDC with 3.6 V input, typical power dissipation is ~350 mW, resulting in ~2.7°C junction-to-board rise - well within the 125°C max junction rating even at 85°C ambient.
TPS65055RSMT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Handheld/Mobile Devices
- Current - Supply:
- -
- Voltage - Supply:
- 2.5V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (4x4)
TPS65055RSMT FAQ
1.How can I place an order for TPS65055RSMT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65055RSMT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65055RSMT reliable?
The price and inventory of TPS65055RSMT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65055RSMT is usually 5 days.
3.What payment methods are accepted for TPS65055RSMT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65055RSMT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65055RSMT?
TPS65055RSMT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65055RSMT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65055RSMT?
For technical support, including TPS65055RSMT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65055RSMT requirements.
6.How does Aetrix verify that TPS65055RSMT is sourced from the original manufacturer or authorized distributors?
All TPS65055RSMT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65055RSMT meets industry standards.
7.What is the process for return or replacement of TPS65055RSMT?
All TPS65055RSMT units undergo pre-shipment inspection (PSI). If there is an issue with TPS65055RSMT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65055RSMT part is unused and in its original packaging.
Return procedure for TPS65055RSMT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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