Texas Instruments TPS65058RGER

Overview

TPS65058RGER from Texas Instruments is a highly integrated power management IC (PMIC) for single-cell Li-Ion/Li-Polymer systems, featuring two 2.25 MHz synchronous step-down converters (DCDC1: 0.6A, DCDC2: 1A) and three low-input-voltage LDOs (VLDO1: 400mA, VLDO2/VLDO3: 200mA each), all in a 4 mm × 4 mm 24-pin QFN package. It delivers dynamic voltage switching for processor core/I/O rails in satellite radio modules and portable embedded systems.

For engineers reviewing the TPS65058RGER datasheet, TPS65058RGER pinout, TPS65058RGER application, or TPS65058RGER equivalent, key selection criteria include dual-converter phase alignment, PFM/PWM mode control via MODE pin, DEF_DCDC2/DEF_LDO programmable output voltages, and integrated reset generation with 100 ms delay.

Technical Context

The TPS65058RGER implements two synchronous buck converters operating at a fixed 2.25 MHz frequency with 180° out-of-phase switching to reduce input RMS current and enable smaller input capacitors. Each converter supports automatic transition between PWM mode (±1% VOUT accuracy) and power-save PFM mode (32 µA total quiescent current) based on load demand.

It integrates three independent LDOs-VLDO1 (400 mA, 3.3 V), VLDO2 (230 mA, 1.8/1.2 V), and VLDO3 (200 mA, 1.8/1.3 V)-with separate enable pins (EN_LDO1–EN_LDO3), programmable output voltages via DEF_LDO, and internal discharge resistors (300 Ω) for fast turn-off. A dedicated reset generator provides open-drain active-low RESET with 100 ms delay after both DC/DC outputs reach 95% of nominal.

Key Specifications

Pinout & Package

TPS65058RGER is housed in a thermally enhanced 4 mm × 4 mm, 24-pin QFN package (RGE) with exposed PowerPAD™ thermal pad connected to AGND/PGND. Pin pitch is 0.5 mm; recommended PCB layout includes thermal vias under the PowerPAD™ for junction temperature control up to 125°C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power management IC applications.

Compared with TPS65023RSBR and TPS65070RSLR, the TPS65058RGER uniquely balances pin-strapped flexibility (DEF_DCDC2/DEF_LDO), compact 24-pin QFN packaging, and ultra-low quiescent current-making it optimal for cost-sensitive, space-constrained, and battery-life-critical designs without communication bus overhead.

Availability

TPS65058RGER is available at Aetrix Electronics and suitable for satellite radio modules, portable media players, industrial handheld terminals, and wearable health monitors requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS65058RGER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC/DC conversion and integrated PMIC design.

The TPS65058 product line targets portable battery-powered applications requiring compact, high-efficiency multi-rail power solutions-specifically optimized for single-cell Li-Ion/Li-Polymer systems in consumer and industrial edge devices.

FAQ

What is the maximum supported output current for each DC/DC converter in the TPS65058RGER?

The TPS65058RGER supports up to 600 mA on DCDC1 (I/O rail) and up to 1000 mA on DCDC2 (core rail), as specified in the Recommended Operating Conditions table. These values assume proper thermal management via the PowerPAD™ and use of recommended 1.5–2.2 µH inductors and 10–22 µF output capacitors. Exceeding these currents may trigger current-limit protection or thermal shutdown.

How does the MODE pin affect operation of the TPS65058RGER?

The MODE pin on the TPS65058RGER selects between automatic power-save mode (MODE = GND) and forced PWM mode (MODE = VIN). In power-save mode, both DC/DC converters switch between PFM (light load, 32 µA IQ) and PWM (heavy load, ±1% accuracy); in forced PWM mode, they operate continuously at 2.25 MHz regardless of load, eliminating low-frequency ripple but increasing light-load quiescent current to ~1.25 mA.

Can the TPS65058RGER generate a system reset signal, and how is it triggered?

Yes, the TPS65058RGER provides an open-drain active-low RESET signal (Pin 10) with a guaranteed 100 ms delay (80–120 ms range). RESET is asserted only after both DCDC1 and DCDC2 outputs reach and maintain ≥95% of their nominal voltages-ensuring reliable power-good sequencing before host processor boot. No external components are required.

What are the output voltage options for VLDO2 and VLDO3 on the TPS65058RGER?

VLDO2 supports 1.8 V (DEF_LDO = high) or 1.2 V (DEF_LDO = low); VLDO3 supports 1.8 V (DEF_LDO = high) or 1.3 V (DEF_LDO = low). These selections are controlled by the same DEF_LDO pin, enabling coordinated voltage configuration across both LDOs. Output voltage accuracy is ±2% over load and temperature, with 280 mV dropout at full rated current.

Is the TPS65058RGER compatible with Li-Polymer battery input voltage ranges?

Yes, the TPS65058RGER accepts 2.5 V to 6 V on VINDCDC1/2-fully covering the discharge profile of single-cell Li-Polymer batteries (typically 4.2 V fully charged down to ~2.7 V cutoff). Its 100% duty-cycle mode maintains regulation even near end-of-discharge, and undervoltage lockout (1.8–2.0 V threshold) prevents deep discharge damage.