Texas Instruments TPS65141PWP
- Part No.:
- TPS65141PWP
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS65141PWP.pdf
- Description:
- IC LCD SUPPLY TFT QUAD 24HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS65141PWP from Texas Instruments is a triple-output LCD power supply IC integrating a 1.6-MHz PWM boost converter (VO1 up to 15 V / 400 mA), a regulated negative charge pump (VO2 down to –12 V / 20 mA), a positive charge pump (VO3 up to 30 V / 20 mA), and a 3.3-V linear regulator controller - all in a single 24-pin HTSSOP package for TFT LCD source/gate driver biasing.
For engineers reviewing the TPS65141PWP datasheet, TPS65141PWP pinout, TPS65141PWP application, or TPS65141PWP equivalent, key selection considerations include its lack of fault-induced shutdown (unlike TPS65140/TPS65145), fixed 1.6-MHz switching frequency enabling compact 4.7-µH inductors and 220-nF flying capacitors, and independent EN/ENR control for flexible power sequencing in notebook and industrial display systems.
Technical Context
The TPS65141PWP implements a voltage-mode PWM boost converter with input feedforward and virtual synchronous operation using an integrated P-MOSFET (Q2) and external Schottky diode, maintaining continuous conduction mode across load range. Its soft-start sequence progresses VO1 → VO2 → VO3 in three timed steps (2048 cycles each), distinct from the shorter ramp in TPS65140/TPS65145.
Unlike TPS65140 and TPS65145, the TPS65141PWP omits output fault detection and shutdown - PG asserts low when any output deviates >10% from nominal, but internal regulation remains active. The linear regulator controller operates independently via ENR and drives an external BJT (e.g., BCP68) to deliver 3.3 V at up to 500 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.8 V - supports direct connection to single-cell Li-ion or 5-V rail without pre-regulation. |
| VO1 Output | Up to 15 V / 400 mA - main boost output powers LCD source drivers; <1% typical accuracy ensures stable gate-on voltage. |
| VO2 Output | Down to –12 V / 20 mA - regulated negative charge pump supplies LCD gate-off voltage with ±36-mV feedback threshold. |
| VO3 Output | Up to 30 V / 20 mA - externally adjustable positive charge pump delivers gate-on voltage with 1.214-V reference and 0.05%/mA load regulation. |
| VO4 Controller | 3.3 V output via external transistor - fixed-set linear regulator controller supports 10–500 mA load with 0.064%/A load regulation. |
| Switching Frequency | 1.6 MHz (±26%) - enables use of small 4.7-µH inductor and 220-nF ceramic flying capacitors, reducing board area and EMI filtering needs. |
| Power Good (PG) | Open-drain output - goes low if VO1, VO2, or VO3 falls >10% from nominal; no auto-shutdown on fault (TPS65141-specific behavior). |
Pinout & Package
TPS65141PWP is housed in a 24-pin HTSSOP (PWP) package measuring 7.80 mm × 4.40 mm with exposed thermal pad connected to PGND. Pin functions are validated per TI SLVS497F Rev F (June 2016) datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1 | Boost converter feedback | Connects to resistor divider from VO1; sets output voltage with 1.146-V internal reference. |
| SW | Boost switch node | Drives external inductor; connects internally to N-MOSFET Q1 (290-mΩ typical rDS(on)) and P-MOSFET Q2. |
| SUP | Supply input for charge pumps | Must be connected to VO1 output only - powers both VO2 and VO3 stages; no external bypass recommended. |
| FB2 | Negative charge pump feedback | Monitors VO2; regulates to –36 mV to +36 mV around ground - enables precise negative rail setting. |
| FB3 | Positive charge pump feedback | Monitors VO3; uses 1.214-V reference for accurate high-voltage generation up to 30 V. |
| EN | Main enable input | Active-high logic control (VIH ≥ 1.5 V); initiates power-on sequencing: VO1 → VO2 → VO3. |
| ENR | LDO controller enable | Independent enable for 3.3-V linear regulator; allows VO4 to remain active during VO1/VO2/VO3 faults. |
| PG | System power good | Open-drain output sinks ≤500 µA; asserts low if any output exceeds ±10% deviation - no latch-up or shutdown. |
| BASE | LDO base drive output | Drives external NPN transistor (e.g., BCP68); delivers up to 27 mA base current for 500-mA VO4 load. |
| DRV | Charge pump driver | Drives external Schottky diodes in VO2/VO3 paths; supports high-frequency (>1 MHz) charge transfer. |
Key Features
| Feature | Design Value |
|---|---|
| Virtual Synchronous Converter | Uses integrated P-MOSFET Q2 + external Schottky diode to sustain CCM at light loads - eliminates switch-node ringing and simplifies compensation. |
| Independent Power Sequencing | Separate EN and ENR pins allow VO4 (3.3 V) to power digital logic before VO1/VO2/VO3 ramp - reduces inrush and enables safe system boot. |
| No Fault-Induced Shutdown | TPS65141-specific behavior: PG signals fault but device continues regulating all outputs - critical for displays requiring uninterrupted bias rails. |
| Integrated Soft Start | Three-stage ramp (2048 cycles per stage) for VO1, VO2, VO3 - prevents input voltage sag and output overshoot during startup. |
| Thermal Protection | 160°C junction shutdown with automatic recovery after cooldown - protects against sustained overload or poor PCB thermal design. |
Applications
| TFT Notebook LCD Panels | Industrial Touchscreen Displays |
|---|---|
Use Scenario: Powering source drivers (VO1), gate-on (VO3), and gate-off (VO2) voltages for 10–17-inch active-matrix TFT panels in portable computing devices. IC Role / Device Role / Timing Role: Single-chip triple-rail generator providing synchronized, sequenced bias supplies with PG monitoring for panel initialization and health reporting. Use Value: Eliminates need for discrete DC/DC converters and charge pumps - reduces BOM count by ≥5 components and saves ≥120 mm² PCB area. |
Use Scenario: Supplying stable gate drive voltages in factory HMIs, medical monitors, and ruggedized human-machine interfaces operating across –40°C to +85°C ambient. IC Role / Device Role / Timing Role: Robust bias supply with independent ENR control ensures 3.3-V logic remains active during VO1/VO2/VO3 transients or faults - maintains MCU communication during display reconfiguration. Use Value: No auto-shutdown on rail fault (TPS65141-specific) prevents unexpected display blackouts in mission-critical UIs. |
| Car Navigation Systems | Portable DVD Players |
Use Scenario: Delivering regulated LCD bias rails in automotive infotainment units subject to wide input voltage swings (cold crank to load dump). IC Role / Device Role / Timing Role: Input voltage range (2.7–5.8 V) and undervoltage lockout (2.4 V typ.) ensure reliable start-up from 12-V battery via buck pre-regulator; PG confirms rail readiness to head unit MCU. Use Value: 1.6-MHz operation minimizes conducted EMI in sensitive RF environments - meets CISPR 25 Class 5 requirements without added shielding. |
Use Scenario: Generating compact, low-noise bias supplies for 7-inch widescreen TFTs in battery-powered consumer AV devices. IC Role / Device Role / Timing Role: Integrated linear regulator controller (VO4) provides clean 3.3-V logic rail from same 5-V input powering VO1 - avoids second LDO and associated dropout loss. Use Value: 220-nF flying capacitors (enabled by 1.6-MHz charge pumps) reduce total capacitance volume by 65% vs. 100-kHz alternatives - extends battery runtime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output LCD supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65140PWP | Includes full fault detection and auto-shutdown on VO1/VO2/VO3 out-of-regulation; identical pinout and package. | Required where system-level safety mandates immediate shutdown on any rail fault (e.g., automotive ASIL-B displays). | Select TPS65140PWP when fault containment is mandatory; TPS65141PWP preferred where continuous bias operation outweighs fault isolation. |
| TPS65145PWP | Lower 1.37-A switch current limit (vs. 2.3 A in TPS65141); optimized for lower-power panels (<200 mA VO1 load). | Better suited for smaller displays (≤5-inch) or designs prioritizing thermal margin over peak current capability. | Choose TPS65145PWP for space-constrained, low-power portable displays; TPS65141PWP supports higher-source-drive-current panels. |
Compared with TPS65140PWP and TPS65145PWP, the TPS65141PWP uniquely sustains regulation during output faults - enabling uninterrupted display operation in non-safety-critical UIs while sharing identical layout, thermal design, and external component values.
Availability
TPS65141PWP is available at Aetrix Electronics and suitable for TFT LCD notebooks, industrial HMIs, and automotive navigation systems requiring stable component supply with guaranteed long-term manufacturability and consistent electrical performance.
Supply support for TPS65141PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in display power solutions.
The TPS6514x product line was designed specifically to consolidate multiple LCD bias rails into one IC for notebook, monitor, and portable display applications - reducing system complexity and improving reliability through integrated sequencing and protection.
FAQ
What is the key functional difference between TPS65141PWP and TPS65140PWP?
The TPS65141PWP does not enter shutdown when any output (VO1, VO2, or VO3) falls outside its regulation window - it only asserts the open-drain PG signal low. In contrast, the TPS65140PWP shuts down all outputs upon detecting such a fault. This makes TPS65141PWP suitable for applications where continuous bias rail operation is prioritized over fault containment. The TPS65141PWP retains identical pinout, package, and external component requirements as the TPS65140PWP.
Does TPS65141PWP support both voltage doubler and tripler modes for VO3?
Yes, the TPS65141PWP supports both modes via the C2–/MODE pin. When the flying capacitor is connected to C2–/MODE, the device operates in tripler mode; when C2–/MODE is grounded and the capacitor is disconnected, it operates in doubler mode. This configuration is confirmed in the Pin Functions table of the SLVS497F datasheet and applies identically to the TPS65141PWP variant.
What external components are required for basic TPS65141PWP operation?
The TPS65141PWP requires an external 4.7-µH power inductor on SW, two 220-nF ceramic flying capacitors (C1+, C1– for VO2; C2+, C2– for VO3), output capacitors (22 µF for VO1, 1 µF for VO4), feedback resistors for VO1/VO2/VO3, and an external NPN transistor (e.g., BCP68) driven by BASE for the 3.3-V linear regulator. No external compensation is needed for default stability, though COMP supports loop tuning if required.
Can the TPS65141PWP's 3.3-V linear regulator controller (VO4) operate independently of the boost and charge pump stages?
Yes - the TPS65141PWP's linear regulator controller is fully independent, controlled by the ENR pin. It can remain enabled (ENR = HIGH) while EN = LOW disables VO1/VO2/VO3, or vice versa. This allows the 3.3-V logic rail to power microcontrollers or interface circuitry even when display bias rails are inactive, supporting low-power standby modes and safe system reset sequences.
What is the maximum allowable output current for VO1 on the TPS65141PWP?
The TPS65141PWP supports up to 400 mA at VO1, as specified in the "Features" section and confirmed in the "Electrical Characteristics" table under VO1 output capability. This rating assumes proper thermal management - the HTSSOP package has a junction-to-ambient thermal resistance (RθJA) of 37.2°C/W, requiring adequate copper pour and airflow to sustain full load at elevated ambient temperatures.
TPS65141PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Applications:
- LCD Monitor, Notebook Display
- Current - Supply:
- 700µA
- Voltage - Supply:
- 2.7V ~ 5.8V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-HTSSOP
TPS65141PWP FAQ
1.How can I place an order for TPS65141PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65141PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65141PWP reliable?
The price and inventory of TPS65141PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65141PWP is usually 5 days.
3.What payment methods are accepted for TPS65141PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65141PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65141PWP?
TPS65141PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65141PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65141PWP?
For technical support, including TPS65141PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65141PWP requirements.
6.How does Aetrix verify that TPS65141PWP is sourced from the original manufacturer or authorized distributors?
All TPS65141PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65141PWP meets industry standards.
7.What is the process for return or replacement of TPS65141PWP?
All TPS65141PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS65141PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65141PWP part is unused and in its original packaging.
Return procedure for TPS65141PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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