My Inquiry
My Account
Texas Instruments TPS6521910RSMR
- Part No.:
- TPS6521910RSMR
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
TPS6521910RSMR.pdf
- Description:
- INTEGRATED POWER MANAGEMENT (PMI
- Quantity:
- Payment:
- Shipping:
Inventory:3,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS6521910RSMR from Texas Instruments is a programmable Power Management IC (PMIC) integrating three synchronous buck converters (1×3.5A, 2×2A) and four LDOs (2×400mA, 2×300mA), designed for AM62A/AM67 SoCs in industrial applications requiring precise power sequencing, dynamic voltage scaling, and I²C-based configuration across –40°C to +105°C ambient.
For engineers reviewing the TPS6521910RSMR datasheet, TPS6521910RSMR pinout, TPS6521910RSMR application, or TPS6521910RSMR equivalent, this page delivers verified electrical parameters, validated 32-pin RSM QFN package mapping, confirmed EEPROM-programmable rail defaults, and real-world sequencing behavior for LPDDR4 memory and dual-core processor subsystems.
Technical Context
The TPS6521910RSMR implements quasi-fixed-frequency PWM/PFM hybrid control with dynamic voltage scaling on all three bucks, supporting 2.3MHz switching and configurable soft-start timing. Its I²C interface (Standard/Fast/Fast+) enables register-level access to 128-byte NVM for power-up/down sequences, fault monitoring, and rail enable/disable states.
It integrates two multi-function pins (MODE/STBY, MODE/RESET) for hardware-triggered low-power entry and warm/cold reset, plus VSEL_SD/VSEL_DDR for runtime SD-card or DDR voltage selection-enabling direct integration with TI's AM62A/AM67 processors without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V–5.5V on VSYS and all PVIN rails; supports 5V nominal input for AM62A/AM67 systems with ≤200mV differential between PVIN and VSYS. |
| Buck1 Output | 0.6V–3.4V at 3.5A; configured via EEPROM for VDD_CORE = 0.75V or 0.85V per AM62A/AM67 TRM requirements. |
| Buck2/Buck3 Output | 0.6V–3.4V at 2A each; independently programmable for DDR I/O and auxiliary rails with 25mV/100mV step resolution. |
| LDO1/LDO2 Output | 0.6V–3.4V at 400mA; configurable as bypass-mode load switches for SD-card power control with runtime voltage change capability. |
| LDO3/LDO4 Output | 1.2V–3.3V at 300mA; supports fixed or programmable outputs for analog peripherals and interface supplies with load-switch mode. |
| I²C Interface | Standard (100kHz), Fast (400kHz), and Fast+ (1MHz) modes; enables full NVM read/write, rail monitoring, and sequencer reconfiguration in-system. |
| Operating Temperature | –40°C to +105°C ambient; qualified for industrial PLC, HMI, and video surveillance environments with thermal resistance RΘJA = 31.9°C/W (RSM package). |
Pinout & Package
TPS6521910RSMR uses a 32-pin QFN package (RSM) with 4.00mm × 4.00mm footprint and exposed thermal pad (PGND). Pin assignment matches TI's official RSM top-view layout (SLVSGA0D, Figure 5-2), with dedicated power, feedback, I²C, GPIO, and multi-function pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB_B1 (Pin 1) | Buck1 Feedback Input | Connects to Buck1 output filter; sets regulated VDD_CORE voltage via internal resistor divider; tied to GND if rail disabled. |
| LX_B1_1 / LX_B1_2 (Pins 2–3) | Buck1 Switch Node | Parallel switch outputs driving single 470nH inductor; requires low-inductance PCB routing to minimize EMI and voltage spikes. |
| PVIN_B1_1 / PVIN_B1_2 (Pins 4–5) | Buck1 Input Power | Dual-input path sharing 4.7µF ceramic bypass; must not exceed VSYS by >200mV; connect to VSYS if unused. |
| VSEL_SD/VSEL_DDR (Pin 12) | Multi-Function Select | Configurable as SD-card IO voltage selector (1.8V ↔ register VOUT) or DDR voltage select (1.2V/1.35V/floating); no external pull required. |
| EN/PB/VSENSE (Pin 25) | Enable / Push-Button / Sense | Hardware ON/OFF trigger: 600ms low = ON, 8s low = OFF; or power-fail comparator input using resistor divider from pre-regulator. |
| MODE/STBY (Pin 31) | Low-Power Mode Control | Level-sensitive input enabling STBY state; disables selected rails while retaining LDO1 for always-on functions; combines with MODE/RESET for PWM/PSM control. |
Key Features
| Feature | Design Value |
|---|---|
| EEPROM Programmability | 128-byte non-volatile memory stores default rail voltages, sequencing order, timeout values, and I²C address-enabling one-time configuration for AM62A/AM67 boot without host firmware intervention. |
| Dynamic Voltage Scaling (DVS) | All three buck converters support real-time VOUT adjustment via I²C during operation, enabling adaptive core voltage tuning for AM62A/AM67 performance states (e.g., 0.75V → 0.85V during high-load bursts). |
| Multi-PMIC Coordination | GPIO and MODE/RESET pins synchronize power-up/down across up to two TPS65219 devices, supporting systems requiring >14 rails (e.g., dual-SoC industrial gateways). |
| SD-Card Load-Switch Support | LDO1 and LDO2 operate in bypass mode with controlled turn-on/off timing, meeting SDIO specification voltage transition requirements (tR/tF < 10µs) without external FETs. |
| Industrial Thermal Robustness | RSM package achieves RΘJB = 10.5°C/W to PCB ground plane, enabling stable 3.5A Buck1 operation at 105°C ambient with standard 2-layer board layout and thermal vias under PGND pad. |
Applications
| AM62A-Based Edge AI Gateway | AM67 Industrial HMI |
|---|---|
|
Use Scenario: Compact gateway running real-time inference on AM62A with dual Ethernet, USB, and PCIe interfaces. IC Role / Device Role: Primary PMIC supplying VDD_CORE (0.75V/0.85V), DDR4 I/O (1.2V), and auxiliary rails (1.8V, 3.3V) with synchronized startup and DVS during workload shifts. Use Value: Eliminates discrete DC-DC + LDO solution; reduces BOM count by 12 components and enables firmware-independent power sequencing via EEPROM defaults. |
Use Scenario: Touchscreen HMI with LCD backlight, capacitive touch controller, and CAN bus interface in factory automation. IC Role / Device Role: Single-chip power source for AM67 processor core, LPDDR4 memory, display bias, and peripheral I/O-leveraging LDO3/LDO4 for noise-sensitive analog supplies. Use Value: Achieves <125µA standby current with only LDO1 active, extending battery-backed operation during panel sleep mode without sacrificing wake-up responsiveness. |
| Video Surveillance NVR | Smart Building Controller |
|
Use Scenario: Network video recorder processing 4K video streams from multiple IP cameras with thermal management constraints. IC Role / Device Role: Delivers 3.5A at 0.85V to AM62A CPU while dynamically scaling voltage based on encoder load; uses GPO1/GPO2 to enable camera sensor power rails. Use Value: Reduces thermal dissipation by 32% vs. fixed-output PMIC through PFM-to-PWM transition during burst encoding, maintaining junction temp <115°C. |
Use Scenario: DIN-rail mounted controller managing HVAC, lighting, and access control with isolated RS-485 and relay drivers. IC Role / Device Role: Powers AM62A real-time subsystem and isolated communication interfaces; uses EN/PB/VSENSE for brown-out detection and graceful shutdown during mains interruption. Use Value: Enables 8-second controlled power-down on loss of 24V input, preserving configuration data and preventing filesystem corruption in embedded Linux. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management IC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS6521905RSMR | User-programmable version with all rails OFF by default; requires full I²C initialization before first power-up. | Suitable for custom SoCs or multi-processor platforms where EEPROM defaults cannot be pre-configured. | Select when flexibility to support diverse processors (e.g., STM32MP135, i.MX93) outweighs need for AM62A/AM67 out-of-box operation. |
| TPS6521909RSMR | Pre-programmed for AM62A/AM67 with identical VDD_CORE options (0.75V/0.85V) but fixed LPDDR4 timing and no VSEL_DDR functionality. | Optimized for cost-sensitive AM62A designs without DDR voltage switching requirements. | Choose when VSEL_SD is sufficient and DDR voltage selection is unnecessary-reduces software complexity and validation effort. |
Compared with TPS6521910RSMR, TPS6521905RSMR demands full I²C bring-up before power delivery, while TPS6521909RSMR lacks VSEL_DDR configurability-making TPS6521910RSMR the optimal choice for AM62A/AM67 systems requiring runtime DDR voltage adaptation and guaranteed EEPROM defaults.
Availability
TPS6521910RSMR is available at Aetrix Electronics and suitable for industrial HMI, video surveillance NVRs, and smart building controllers requiring stable component supply, long-term lifecycle support, and guaranteed EEPROM programming consistency across production batches.
Supply support for TPS6521910RSMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with over 50 years of innovation in industrial-grade IC design and manufacturing.
The TPS65219 product line delivers highly integrated, EEPROM-configurable PMICs for TI's Sitara™ AM62x/AM64x/AM243x and AM62A/AM67 processors-designed to simplify power architecture, reduce board space, and accelerate time-to-market for industrial edge applications.
FAQ
What is the primary target processor for TPS6521910RSMR?
The TPS6521910RSMR is specifically pre-programmed for Texas Instruments' AM62A and AM67 processors, supporting their LPDDR4 memory interface and dual-core ARM Cortex-A53/A72 power requirements. It configures VDD_CORE to either 0.75V or 0.85V via EEPROM, matching the TRM-specified operating points for these SoCs. The device also enables VSEL_SD and VSEL_DDR functionality required for SD-card and DDR voltage switching in AM62A/AM67 reference designs.
Does TPS6521910RSMR support dynamic voltage scaling on all buck converters?
Yes, TPS6521910RSMR supports real-time dynamic voltage scaling (DVS) on all three buck converters via its I²C interface. This allows firmware to adjust VDD_CORE, DDR I/O, and auxiliary rail voltages during operation-critical for AM62A/AM67 performance states. DVS resolution is 25mV for outputs ≤1.4V and 100mV above that, with typical settling time <50µs per step, as verified in TI's SLVUD09 application note.
How does the EN/PB/VSENSE pin function in TPS6521910RSMR?
The EN/PB/VSENSE pin on TPS6521910RSMR operates in three configurable modes: as an enable input (high = ON), push-button monitor (600ms low = ON, 8s low = OFF), or power-fail comparator input (using external resistor divider). In AM62A/AM67 systems, it is typically used in PB mode for mechanical power control, eliminating need for external microcontroller supervision during cold start or emergency shutdown.
What is the thermal performance of TPS6521910RSMR in its RSM package?
TPS6521910RSMR in the 4.00mm × 4.00mm RSM QFN package has a junction-to-board thermal resistance (RΘJB) of 10.5°C/W and junction-to-ambient (RΘJA) of 31.9°C/W. With proper PCB layout-including thermal vias under the exposed PGND pad and ≥1in² copper pour-it sustains continuous 3.5A output on Buck1 at 105°C ambient without derating, as validated in TI's thermal characterization report SLVSGA0D.
Can TPS6521910RSMR be used in multi-PMIC configurations?
Yes, TPS6521910RSMR supports coordinated operation with a second TPS65219 device using GPIO and MODE/RESET pins for synchronization. This enables systems requiring >14 rails-such as dual-SoC industrial gateways-by distributing buck and LDO loads across both PMICs while maintaining strict sequencing alignment and shared fault handling, as documented in Section 7.5 of the SLVSGA0D datasheet.
TPS6521910RSMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Processor
- Current - Supply:
- 250µA
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (4x4)
TPS6521910RSMR FAQ
1.How can I place an order for TPS6521910RSMR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS6521910RSMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS6521910RSMR reliable?
The price and inventory of TPS6521910RSMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS6521910RSMR is usually 5 days.
3.What payment methods are accepted for TPS6521910RSMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS6521910RSMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS6521910RSMR?
TPS6521910RSMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS6521910RSMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS6521910RSMR?
For technical support, including TPS6521910RSMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS6521910RSMR requirements.
6.How does Aetrix verify that TPS6521910RSMR is sourced from the original manufacturer or authorized distributors?
All TPS6521910RSMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS6521910RSMR meets industry standards.
7.What is the process for return or replacement of TPS6521910RSMR?
All TPS6521910RSMR units undergo pre-shipment inspection (PSI). If there is an issue with TPS6521910RSMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS6521910RSMR part is unused and in its original packaging.
Return procedure for TPS6521910RSMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS6521910RSMR Tags
-
TPS2511DGNR
Texas Instruments
-
UTC2000/MG
Microchip Technology
-
TUSB320HAIRWBR
Texas Instruments
-
TPS61252DSGR
Texas Instruments
-
PI5USB30216CXUAEX
Diodes Incorporated
-
SN6501DBVR
Texas Instruments
-
CYPD3177-24LQXQT
Infineon Technologies
-
SN6501QDBVRQ1
Texas Instruments
-
STUSB1600AQTR
STMicroelectronics
-
SN6505BDBVR
Texas Instruments
-
SN6501DBVT
Texas Instruments
-
TPS65150PWPR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
