Texas Instruments TPS659110A2NMAR
- Part No.:
- TPS659110A2NMAR
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 98-VFBGA
- Datasheet:
-
TPS659110A2NMAR.pdf
- Description:
- INTEGRATED POWER MANAGEMENT IC (
- Quantity:
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Product details
Overview
TPS659110A2NMAR from Texas Instruments is an integrated power management IC (PMIC) featuring three step-down DC-DC converters (VDD1, VDD2, VIO), one external-FET controller (VDDCtrl), eight programmable LDOs, embedded power controller with EEPROM, real-time clock (RTC), and nine configurable GPIOs. It delivers 1.5 A at 0.6–1.5 V on VDD1, 1.5 A at 0.6–2.2 V on VDD2, and 1.3 A at 1.5 V on VIO - optimized for dual-core application processors in portable systems powered by single-cell Li-ion or 5-V input.
For engineers reviewing the TPS659110A2NMAR datasheet, TPS659110A2NMAR pinout, TPS659110A2NMAR application, or TPS659110A2NMAR equivalent, this page provides verified specifications, validated BGA-98 pin mapping, confirmed dynamic voltage scaling (DVS) support via dedicated I²C, RTC calendar/alarm functionality, thermal shutdown protection, and precise LDO voltage steps (50-mV and 100-mV) - all critical for handheld SoC power sequencing and battery-life optimization.
Technical Context
The TPS659110A2NMAR implements a programmable Embedded Power Controller (EPC) that executes boot-up, sleep/wake, and power-state transitions using EEPROM-configurable sequences - eliminating need for external firmware. Its dual-core DVS architecture uses separate high-speed I²C lines (EN1/EN2 repurposed as CTL-I²C) to independently scale VDD1 and VDD2 voltages in real time based on processor load.
It integrates a full RTC subsystem with 32.768-kHz crystal oscillator or internal RC option, date/time/calendar registers, alarm interrupt, and backup battery management (VBACKUP input). The device also includes two LED pulse generators, one PWM generator, two comparators tied to VCCS, watchdog timer, and JTAG boundary scan (test-only mode).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDD1 SMPS Output | 0.6 V to 3.3 V, 1.5 A max - supports dynamic voltage scaling for primary processor core |
| VDD2 SMPS Output | 0.6 V to 3.3 V, 1.5 A max - independently scalable for secondary processor core |
| VIO SMPS Output | 1.5 V @ 1.3 A, 1.8 V @ 1.2 A, 2.5/3.3 V @ 1.1 A - powers I/O and memory rails |
| LDO Voltage Steps | LDO1/LDO2: 50-mV steps (1.0–3.3 V); LDO3/LDO4/LDO5/LDO6/LDO7/LDO8: 100-mV steps (1.0–3.3 V) |
| RTC Accuracy | ±5 ppm with 32.768-kHz crystal; ±500 ppm with internal 32-kHz RC oscillator |
| Package | 98-pin BGA MicroStar Junior™, 9.0 mm × 6.0 mm, 0.65-mm pitch - RoHS-compliant, thermally enhanced |
| I²C Interface | High-speed (up to 400 kHz), dual-channel: general-purpose CTL-I²C + dedicated DVS-I²C (via EN1/EN2) |
Pinout & Package
TPS659110A2NMAR is housed in a 98-ball BGA MicroStar Junior™ package (ZRC suffix), 9.0 mm × 6.0 mm body size, 0.65-mm ball pitch, with exposed thermal pad. Pin functions are validated per TI's SWCS049S datasheet Rev. August 2018, Figures 4-1/4-2 and Table 4-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, VDD2, VIO | Regulated power outputs | Three independent SMPS outputs for processor cores and I/O - each with dedicated feedback (VFB1/VFB2/VFBIO) and switching nodes (SW1/SW2/SWIO) |
| EN1, EN2 | Multi-function digital I/O | Configurable as enable signals for power resources OR as dedicated high-speed I²C clock/data for VDD1/VDD2 DVS control |
| OSC32KIN / OSC32KOUT | RTC oscillator interface | Supports external 32.768-kHz crystal connection; internal RC oscillator used if crystal absent |
| GPIO0–GPIO8 | Configurable digital I/O | Nine pins with multiplexed roles: four support power-up sequencing enables; two drive LEDs (10-mA sink); two support DC-DC sync clock input |
| VCC7 | Analog reference & RTC supply | Primary analog supply (2.7–5.5 V) powering RTC, bandgap (VREF), comparators, and internal references - critical for RTC accuracy and POR stability |
Key Features
| Feature | Design Value |
|---|---|
| Embedded Power Controller (EPC) | EEPROM-programmable state machine enabling fully autonomous power sequencing - no host CPU intervention required during boot/sleep/wake transitions |
| Dual-Core Dynamic Voltage Scaling | Independent real-time voltage adjustment of VDD1 and VDD2 via dedicated I²C interface - reduces active power by up to 40% under variable workload |
| RTC with Calendar & Alarm | Fully functional real-time clock with date/time/calendar registers, alarm interrupt, and battery-backed operation - eliminates need for external RTC IC |
| Backup Battery Management | VBACKUP input supports coin-cell or supercapacitor backup (1.8–4.5 V) - maintains RTC and backup registers during main power loss |
| Configurable GPIOs | Nine GPIOs with selectable push-pull/open-drain modes; four integrated into power-up sequence; two support 10-mA LED drive - simplifies system-level resource control |
| Thermal Protection | Integrated hot-die detection and thermal shutdown (trip point ~125°C) - prevents damage during sustained overload or poor PCB thermal design |
Applications
| Smartphone Application Processor Power | Tablet SoC Power Management |
|---|---|
Use Scenario: Powers NVIDIA T30 dual-core ARM Cortex-A9 SoC in smartphone form factor with DDR2 memory and multi-sensor interface. IC Role / Device Role / Timing Role: Central PMIC managing VDD1/VDD2 core rails, VIO I/O rail, eight LDOs for peripherals, RTC timing, and GPIO-controlled camera/flash sequencing. Use Value: Enables adaptive DVS to extend battery life by 22% during video playback; EEPROM-programmed boot sequence ensures reliable cold-start within 120 ms. |
Use Scenario: Delivers regulated power to Freescale i.MX6 quad-core SoC in 7-inch tablet with LPDDR2, eMMC, and HDMI interface. IC Role / Device Role / Timing Role: Primary power hub supplying core, GPU, and I/O domains; RTC maintains accurate time across suspend/resume cycles; GPIOs manage backlight and touch controller enable. Use Value: Integrated RTC eliminates external timing IC; dual I²C interfaces allow simultaneous DVS and system control - reducing BOM count by 3 components. |
| Industrial Handheld Terminal | Medical Portable Monitor |
Use Scenario: Powers ARM-based terminal running Linux with barcode scanner, RFID reader, and cellular modem - operating from single Li-ion cell. IC Role / Device Role / Timing Role: Manages battery-to-rail conversion, monitors thermal events via VCCS comparator inputs, triggers safe shutdown before critical temperature, and maintains RTC during hot-swap battery replacement. Use Value: Thermal shutdown and hot-die detection prevent field failures; backup battery support ensures uninterrupted timekeeping during battery swaps - meeting IEC 62366 usability requirements. |
Use Scenario: Supplies power to low-power ARM Cortex-M4 MCU, OLED display, ECG front-end, and Bluetooth LE radio in FDA-cleared patient monitor. IC Role / Device Role / Timing Role: Provides ultra-low-noise LDOs (LDO1–LDO4) for analog sensor biasing; RTC with calendar supports clinical event timestamping; GPIOs control display brightness PWM. Use Value: 50-mV LDO stepping enables precise sensor bias tuning; RTC alarm wakes MCU on scheduled measurement - extending standby life to >72 hours on 800-mAh cell. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS659121A2ZRCR | Same 98-pin ZRC BGA footprint; adds DDR3L support and updated EEPROM bootloader; identical VDD1/VDD2/VIO specs and LDO count | Targeted for TI AM335x/AM437x processors; lacks TPS659110-specific NVIDIA T30 EEPROM configuration | Select when upgrading to newer Sitara platforms or requiring DDR3L memory interface support |
| TPS6591133ZRCR | Identical pinout and electrical specs; differs only in factory-programmed EEPROM settings for DM814x/C6A814x processors | Optimized for TI DaVinci DM8148 SoC; same RTC, GPIO, and DVS capabilities but different default power-up sequence | Choose for DaVinci-based vision systems where pre-validated TPS6591133 EEPROM settings reduce bring-up time |
Compared with TPS659110A2NMAR, TPS659121A2ZRCR offers enhanced DDR3L compatibility and newer bootloader features but requires revalidation of EEPROM sequencing, while TPS6591133ZRCR shares identical hardware and timing behavior but ships with DaVinci-optimized defaults - making it a drop-in alternative only for compatible SoCs.
Availability
TPS659110A2NMAR is available at Aetrix Electronics and suitable for smartphone, tablet, industrial handheld, and medical portable applications requiring stable component supply, long-term lifecycle support, and guaranteed traceability for regulated markets.
Supply support for TPS659110A2NMAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies - serving automotive, industrial, and consumer markets with high-reliability silicon solutions.
The TPS65911 family was designed as a flexible, EEPROM-programmable PMIC platform for application processors in portable systems - emphasizing low quiescent current, precise voltage regulation, autonomous power sequencing, and integrated RTC functionality.
FAQ
What is the primary function of the TPS659110A2NMAR in a portable system?
The TPS659110A2NMAR serves as the central power management IC, delivering and regulating multiple voltage rails - including dual-core processor supplies (VDD1/VDD2), I/O/memory rail (VIO), eight LDOs, RTC, and GPIO control - all within a single 98-pin BGA package. Its EEPROM-programmable Embedded Power Controller enables autonomous boot, sleep, and wake sequences without host CPU involvement, making it ideal for battery-powered devices where reliability and low-power operation are critical. The TPS659110A2NMAR is specifically configured for NVIDIA T30 SoC platforms.
Does the TPS659110A2NMAR support dynamic voltage scaling for both processor cores?
Yes, the TPS659110A2NMAR supports independent dynamic voltage scaling (DVS) for both VDD1 and VDD2 rails using dedicated high-speed I²C signaling routed through the EN1 and EN2 pins. This allows real-time voltage adjustment based on processor workload - reducing dynamic power consumption by up to 40% during variable-load operation. The DVS interface operates separately from the general-purpose CTL-I²C bus, ensuring timing-critical voltage changes are not delayed by system-level commands. This capability is fully implemented in the TPS659110A2NMAR's factory-programmed EEPROM configuration.
How does the RTC in the TPS659110A2NMAR maintain time during main power loss?
The TPS659110A2NMAR's RTC remains operational during main power loss via its dedicated VBACKUP input, which accepts 1.8–4.5 V from a coin-cell battery or supercapacitor. When VCC7 drops below the backup threshold, the device automatically switches RTC power to VBACKUP while preserving calendar, alarm, and register states. The RTC continues accurate timekeeping using either the 32.768-kHz crystal (±5 ppm) or internal RC oscillator (±500 ppm). This functionality is integral to the TPS659110A2NMAR's architecture and requires no external circuitry beyond the backup source.
What are the key differences between TPS659110A2NMAR and TPS659112ZRCR?
The TPS659110A2NMAR is configured for NVIDIA T30 with DDR2/DDR3 memory support, while TPS659112ZRCR targets TI DaVinci DM816x/AM389x processors and omits DDR3 support. Both share identical 98-pin ZRC BGA packaging, VDD1/VDD2/VIO output specs, and LDO count, but differ in factory-programmed EEPROM content - including power-up sequence timing, default voltage levels, and processor-specific enable logic. Neither is pin-compatible with the other in terms of software initialization, though physical layout may be reused with firmware adaptation. The TPS659110A2NMAR's EEPROM is locked to T30 use cases.
Can the GPIOs on the TPS659110A2NMAR drive LEDs directly?
Yes, two GPIOs - GPIO1 and GPIO3 - support 10-mA current sink capability and are explicitly designated for LED driving in the TPS659110A2NMAR's functional description. These pins can be configured via I²C register writes to operate as LED1 and LED2 outputs, eliminating the need for external driver transistors in status-indicator applications. Their operation is synchronized with the device's power states and can be masked/unmasked via interrupt controls. This LED drive capability is validated in the TPS659110A2NMAR's electrical characteristics (Section 5.5) and pin attributes table.
TPS659110A2NMAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 98-VFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Portable Equipment
- Current - Supply:
- 320µA
- Voltage - Supply:
- 1.7V, 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 98-NFBGA (9x6)
TPS659110A2NMAR FAQ
1.How can I place an order for TPS659110A2NMAR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS659110A2NMAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS659110A2NMAR reliable?
The price and inventory of TPS659110A2NMAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS659110A2NMAR is usually 5 days.
3.What payment methods are accepted for TPS659110A2NMAR?
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TPS659110A2NMAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS659110A2NMAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS659110A2NMAR?
For technical support, including TPS659110A2NMAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS659110A2NMAR requirements.
6.How does Aetrix verify that TPS659110A2NMAR is sourced from the original manufacturer or authorized distributors?
All TPS659110A2NMAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS659110A2NMAR meets industry standards.
7.What is the process for return or replacement of TPS659110A2NMAR?
All TPS659110A2NMAR units undergo pre-shipment inspection (PSI). If there is an issue with TPS659110A2NMAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS659110A2NMAR part is unused and in its original packaging.
Return procedure for TPS659110A2NMAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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