Texas Instruments TPS659112A2NMAR
- Part No.:
- TPS659112A2NMAR
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 98-VFBGA
- Datasheet:
-
TPS659112A2NMAR.pdf
- Description:
- INTEGRATED POWER MANAGEMENT IC (
- Quantity:
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Product details
Overview
TPS659112A2NMAR from Texas Instruments is an integrated power management IC (PMIC) featuring three step-down DC-DC converters (VDD1, VDD2, VIO), one external-FET controller (VDDCtrl), eight programmable LDOs, embedded power controller with EEPROM, real-time clock (RTC), and nine configurable GPIOs. It delivers 1.5 A at 0.6–1.5 V on VDD1, 1.5 A at 0.6–2.2 V on VDD2, and 1.3 A at 1.5 V on VIO - optimized for dual-core application processors in portable systems powered by single-cell Li-ion or 5-V input.
For engineers reviewing the TPS659112A2NMAR datasheet, TPS659112A2NMAR pinout, TPS659112A2NMAR application, or TPS659112A2NMAR equivalent, this device supports dynamic voltage scaling via dedicated I²C interface, thermal shutdown with hot-die detection, 32.768-kHz RTC oscillator (crystal or internal RC), and programmable power sequencing - critical for OMAP/ARM-based handhelds, industrial HMIs, and embedded vision platforms requiring multi-rail coordination and low-quiescent-power sleep states.
Technical Context
The TPS659112A2NMAR implements a hierarchical power architecture: two core SMPS (VDD1/VDD2) support adaptive voltage scaling under I²C control, while VIO supplies I/O and memory rails; the VDDCtrl controller drives external high-current FETs for flexible rail extension. Its embedded power controller (EPC) executes EEPROM-programmable boot-up, sleep, and reset sequences independent of host processor intervention.
Real-time clock functionality includes calendar, alarm, and backup register retention via VRTC LDO (2.5 V, 10 µA quiescent), supported by dedicated 32-kHz crystal interface (OSC32KIN/OSC32KOUT) and CLK32KOUT output. Nine GPIOs provide multiplexed roles - including LED drive (10 mA sink), interrupt generation, enable signaling, and DC-DC synchronization - all managed through register-mapped I²C access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VDD1 SMPS Output | 0.6–3.3 V, 1.5 A max - powers primary processor core with DVS support |
| VDD2 SMPS Output | 0.6–3.3 V, 1.5 A max - powers secondary processor core with independent DVS |
| VIO SMPS Output | 1.5 V @ 1.3 A, 1.8 V @ 1.2 A, 2.5/3.3 V @ 1.1 A - supplies system I/O and DDR memory |
| LDO Count & Range | Eight user-programmable LDOs: five at 1–3.3 V (100-mV steps), three at 1–3.3 V (50-mV steps) |
| RTC Accuracy | 32.768-kHz crystal or 32-kHz internal RC oscillator - enables calendar/timekeeping with alarm |
| I²C Interface | High-speed (up to 400 kHz) CTL-I²C + optional EN1/EN2 dual-purpose I²C bus for voltage scaling |
| Package | 98-pin BGA MicroStar Junior™ (9.0 × 6.0 mm, 0.65-mm pitch) - supports high-density portable PCB layouts |
Pinout & Package
TPS659112A2NMAR is housed in a 98-pin ZRC Plastic Ball-Grid Array (BGA) package measuring 9.0 mm × 6.0 mm with 0.65-mm ball pitch. The package features dedicated analog/digital ground planes (AGND, DGND, GNDC), isolated power inputs per regulator domain (VCC1–VCC7, V5IN, VBACKUP), and functional ball assignments verified per TI's SWCS049S datasheet Figures 4-1 and 4-2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD1, VDD2, VIO | Regulated power outputs | Core processor, secondary core, and I/O/memory supply rails with current capability up to 1.5 A |
| SW1, SW2, SWIO | Switch-node outputs | Internal high-side FET switching nodes - require external inductor and output capacitor |
| VFB1, VFB2, VFBIO | Feedback inputs | Resistor-divider inputs setting output voltage; internal 5-µA pull-down aids stability during disable |
| EN1, EN2 | Enable / I²C bidirectional pins | Configurable as hardware enables or dedicated I²C clock/data lines for VDD1/VDD2 voltage scaling |
| OSC32KIN / OSC32KOUT | 32-kHz crystal interface | Connects to 32.768-kHz tuning-fork crystal; supports RTC timing with ±20 ppm accuracy |
| GPIO0–GPIO8 | Configurable digital I/O | Nine pins supporting push-pull/OD modes; four used in power-up sequence, two drive LEDs (10 mA sink) |
Key Features
| Feature | Design Value |
|---|---|
| Embedded Power Controller (EPC) | EEPROM-programmable state machine enabling autonomous boot, sleep, and reset sequencing without host CPU involvement |
| Dual-Core Dynamic Voltage Scaling | Independent I²C-controlled voltage adjustment on VDD1 and VDD2 - reduces dynamic power by >40% during low-load operation |
| RTC with Calendar & Alarm | Full date/time/calendar with alarm interrupt; retains time across main power loss using VBACKUP or VRTC LDO |
| Programmable LDO Setpoints | All eight LDOs digitally adjustable via I²C: five at 100-mV increments, three at 50-mV increments - eliminates external resistor networks |
| Thermal Monitoring | Integrated die temperature sensor with programmable hot-die detection and automatic thermal shutdown at 125°C junction |
| Multi-Function GPIOs | Nine GPIOs support LED pulse generation, comparator-triggered interrupts, DC-DC sync clock input, and external resource enable control |
Applications
| Smartphone Application Processor Power | Industrial HMI Display Controller |
|---|---|
|
Use Scenario: Dual-core ARM Cortex-A9 SoC (e.g., TI AM3894) operating in burst-mode video decode with dynamic frequency scaling. IC Role / Device Role / Timing Role: Central PMIC managing VDD1/VDD2 core rails, VIO I/O rail, RTC timing, and GPIO-driven backlight control. Use Value: Enables sub-100 µA deep-sleep current via EEPROM-configured sequencing and RTC wake-on-alarm - extends battery life beyond 72 hours. |
Use Scenario: Ruggedized touchscreen HMI running Linux on DM8168 with Ethernet, USB, and LCD interfaces. IC Role / Device Role / Timing Role: Single-chip power hub delivering regulated rails for CPU, DDR3, FPGA I/O, display bias, and RTC backup. Use Value: Eliminates six discrete regulators and sequencer ICs; reduces BOM count by 32% while maintaining <±1% output regulation across –40°C to +85°C. |
| Embedded Vision Camera Module | Medical Portable Diagnostic Device |
|
Use Scenario: Low-power stereo camera module with MIPI CSI-2 interface, image signal processor, and flash LED strobe. IC Role / Device Role / Timing Role: Supplies VDD1/VDD2 to ISP cores, VIO to MIPI PHY, LDOs to sensors and flash drivers, and RTC for timestamping. Use Value: Synchronizes DC-DC switching to 3-MHz external clock - suppresses EMI in sensitive analog imaging paths by >15 dB. |
Use Scenario: Battery-powered ECG monitor with Bluetooth LE, OLED display, and precision analog front-end. IC Role / Device Role / Timing Role: Powers mixed-signal SoC, ADC reference, display driver, BLE radio, and RTC with ultra-low-noise LDOs. Use Value: VRTC LDO (2.5 V, 10 µA IQ) and backup registers retain patient session data during battery swap - meets IEC 62304 Class C requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS659122A2NMAR | Same pinout and register map; adds DDR3L memory power support and updated EEPROM firmware for newer TI processors | Targeted at AM57xx/66AK2Gx SoCs requiring DDR3L termination and enhanced thermal monitoring | Select when upgrading from AM38xx/DM81xx platforms to AM57xx or needing DDR3L compatibility |
| TPS65910A3ZQCR | 96-pin BGA (vs. 98-pin); lacks VDDCtrl controller and second RTC alarm; reduced GPIO count (7 vs. 9) | Suitable for simpler OMAP4/AM35xx designs without external high-current FET requirements | Choose for cost-sensitive OMAP4-based tablets where VDDCtrl and dual RTC alarms are unnecessary |
Compared with TPS659112A2NMAR, TPS659122A2NMAR offers backward-compatible pinout and firmware enhancements for next-gen processors, while TPS65910A3ZQCR provides a lower-cost, functionally trimmed alternative for legacy OMAP4 systems - neither is pin-compatible without layout revision due to ball count and placement differences.
Availability
TPS659112A2NMAR is available at Aetrix Electronics and suitable for smartphone application processor power, industrial HMI display controllers, embedded vision camera modules, and medical portable diagnostic devices requiring stable component supply across extended product lifecycles.
Supply support for TPS659112A2NMAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in energy-efficient IC design.
The TPS65911 family was engineered specifically for OMAP/ARM-based portable systems requiring tightly coordinated multi-rail power sequencing, dynamic voltage scaling, and integrated RTC - targeting handheld computing, automotive infotainment, and industrial edge devices.
FAQ
What is the maximum output current capability of the VDD1 and VDD2 DC-DC converters in the TPS659112A2NMAR?
The TPS659112A2NMAR supports up to 1.5 A continuous output current on both VDD1 and VDD2 step-down converters. Each operates across 0.6 V to 3.3 V with programmable voltage steps, and their current capability is validated per TI's SWCS049S datasheet Section 5.14 and 5.15 - including thermal derating curves for ambient temperatures up to +85°C. This rating assumes proper PCB layout with adequate copper area and thermal vias.
Does the TPS659112A2NMAR support external crystal oscillators for its real-time clock?
Yes, the TPS659112A2NMAR supports a 32.768-kHz external crystal oscillator via dedicated OSC32KIN and OSC32KOUT pins. It also includes an internal 32-kHz RC oscillator as fallback. Crystal operation achieves ±20 ppm accuracy over temperature and enables full RTC calendar, alarm, and timestamping functions - confirmed in Section 5.10 and Figure 6-10 of the SWCS049S datasheet.
How many LDO regulators does the TPS659112A2NMAR integrate, and what are their voltage resolution options?
The TPS659112A2NMAR integrates eight user-programmable LDO regulators. Five (LDO3, LDO5–LDO8) support 1.0–3.3 V in 100-mV steps; three (LDO1, LDO2, LDO4) support 1.0–3.3 V in 50-mV steps. All are controlled via I²C register writes, and their output voltages are set using SEL bits documented in Tables 6-35 through 6-44 of the SWCS049S datasheet.
Can the EN1 and EN2 pins of the TPS659112A2NMAR be used simultaneously for hardware enable and I²C communication?
No - EN1 and EN2 are multiplexed pins: they operate either as independent hardware enable signals for power resources or as dedicated I²C clock/data lines for VDD1/VDD2 voltage scaling, but not both simultaneously. Pin function is selected at boot via EEPROM configuration or strap options; this dual-mode behavior is defined in Section 1.1 Features and Table 4-1 of the SWCS049S datasheet.
What thermal protection features are implemented in the TPS659112A2NMAR?
The TPS659112A2NMAR includes integrated thermal shutdown that activates at 125°C junction temperature, plus programmable hot-die detection with interrupt reporting via INT1. Thermal metrics (θJA = 32.5°C/W, θJC = 3.2°C/W) are specified in Section 5.4, and thermal monitoring is managed by the embedded power controller - allowing custom trip thresholds and response actions stored in EEPROM per Section 6.13.
TPS659112A2NMAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 98-VFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Portable Equipment
- Current - Supply:
- 320µA
- Voltage - Supply:
- 1.7V, 2.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 98-NFBGA (9x6)
TPS659112A2NMAR FAQ
1.How can I place an order for TPS659112A2NMAR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS659112A2NMAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS659112A2NMAR reliable?
The price and inventory of TPS659112A2NMAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS659112A2NMAR is usually 5 days.
3.What payment methods are accepted for TPS659112A2NMAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS659112A2NMAR transactions.
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4.How is shipping managed for TPS659112A2NMAR?
TPS659112A2NMAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS659112A2NMAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS659112A2NMAR?
For technical support, including TPS659112A2NMAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS659112A2NMAR requirements.
6.How does Aetrix verify that TPS659112A2NMAR is sourced from the original manufacturer or authorized distributors?
All TPS659112A2NMAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS659112A2NMAR meets industry standards.
7.What is the process for return or replacement of TPS659112A2NMAR?
All TPS659112A2NMAR units undergo pre-shipment inspection (PSI). If there is an issue with TPS659112A2NMAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS659112A2NMAR part is unused and in its original packaging.
Return procedure for TPS659112A2NMAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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