Texas Instruments TPS659118A2ZRCR

Overview

TPS659118A2ZRCR from Texas Instruments is a highly integrated power-management IC (PMIC) designed for the 66AK2G02 multicore SoC, delivering 12 regulated power rails including three DC-DC converters (VDD1: 0.9 V/2 A, VDD2: 1.35 V/1.2 A, VIO: 3.3 V/1.5 A) and eight LDOs with factory-programmed EEPROM-based power-up sequencing. It supports dynamic voltage scaling, I²C-controlled configuration, and real-time thermal monitoring in industrial and embedded communications systems.

For engineers reviewing the TPS659118A2ZRCR datasheet, TPS659118A2ZRCR pinout, TPS659118A2ZRCR application, or TPS659118A2ZRCR equivalent, key selection considerations include its fixed 7×7 mm QFN-48 package, EEPROM-configured boot sequence (e.g., VIO at slot 2, VDD1 at slot 7), GPIO programmability (GPIO0 push-pull, GPIO2/6/7 open-drain), and support for both internal RC and external 32.768 kHz crystal clock sources.

Technical Context

The TPS659118A2ZRCR implements a hierarchical power architecture with three synchronous buck converters operating in pulse-skipping mode for efficiency at light loads, and eight low-noise LDOs optimized for processor core, I/O, memory, and peripheral rail requirements. Its EEPROM stores immutable boot timing slots (2 ms per slot), voltage setpoints, and interrupt mask configurations.

Power sequencing is fully deterministic: VIO, LDO5–LDO8, and GPIO2 power up first (slot 2); followed by LDO1–LDO4 and GPIO7 (slot 4); then VDD2 and GPIO0 (slot 5); VDDCTRL and GPIO6 (slot 6); VDD1 and CLK32KOUT (slot 7); and finally NRESPWRON (slot 10). All rails are monitored via dedicated PGOOD signals and thermal interrupts (HOTDIE_IT).

Key Specifications

Pinout & Package

TPS659118A2ZRCR uses a 48-pin QFN package (ZRC suffix) with 0.5 mm pitch and exposed thermal pad (pin 49). Pin functions are defined per TI SWCU176 and confirmed on official TI product folder.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Compared with TPS659118A2ZRCR, TPS659121ZQMR offers tighter voltage tolerance but reduced current capability and missing GPIOs, while TPS65917ZQMR adds features irrelevant to 66AK2G02 and introduces timing risks due to altered boot slot allocation.

Availability

TPS659118A2ZRCR is available at Aetrix Electronics and suitable for industrial edge gateways, multicore DSP systems, secure communications modules, medical imaging subsystems, and radar processing units requiring stable component supply across extended product lifecycles.

Supply support for TPS659118A2ZRCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies since 1930.

The TPS6591xx family was engineered specifically to support TI's KeyStone II multicore processors like the 66AK2G02, integrating tightly coupled power sequencing, thermal safety, and I²C configurability into a single chip for space-constrained, high-reliability embedded systems.

FAQ

What is the factory-default voltage setting for VDD1 on the TPS659118A2ZRCR?

The TPS659118A2ZRCR has VDD1 factory-configured to 0.9 V (±1.5%) with pulse-skipping mode enabled, as specified in EEPROM register VDD1_OP_REG/SEL. This matches the 66AK2G02 core voltage requirement at nominal frequency and is confirmed in Table 2 of SWCU176. The TPS659118A2ZRCR supports dynamic adjustment via I²C, but the boot-time value is fixed in EEPROM and cannot be changed without reprogramming the one-time programmable memory.

Does the TPS659118A2ZRCR support external 32.768 kHz crystal operation?

Yes, the TPS659118A2ZRCR supports external 32.768 kHz crystal operation on OSC32KIN/OSC32KOUT pins. However, the default EEPROM setting (CK32K_CTRL = 1 in DEVCTRL_REG) selects the internal RC oscillator for boot. To use the crystal, software must write CK32K_CTRL = 0 after power-up, and the crystal must meet TI's specified 12 pF load capacitance requirement per SWCU176 Figure 2.

How many GPIOs does the TPS659118A2ZRCR provide, and what are their electrical types?

The TPS659118A2ZRCR provides eight GPIOs (GPIO0–GPIO7). GPIO0 is factory-configured as a push-pull output referenced to VCC7; GPIO2, GPIO6, and GPIO7 are open-drain outputs requiring external pullups; GPIO1, GPIO3–GPIO5, and GPIO8 are reserved or unused in the 66AK2G02 configuration per SWCU176. All GPIOs are programmable via GPIOx_REG registers and power up in defined states per EEPROM slot assignment.

What is the purpose of the NRESPWRON pin on the TPS659118A2ZRCR?

The NRESPWRON pin on the TPS659118A2ZRCR is an active-low reset output that signals the processor when the PMIC enters or exits the ACTIVE state. It powers up at slot 10 in the EEPROM sequence and remains asserted until all regulated rails are stable and PGOOD signals are valid. This pin synchronizes 66AK2G02's PORn assertion and is essential for reliable boot handoff, as documented in Figure 3 and Section 3.1 of SWCU176.

Can the TPS659118A2ZRCR be used without connecting a backup battery to VBACKUP?

Yes, the TPS659118A2ZRCR can operate without a backup battery. Per SWCU176 Section 2 notes, if no backup battery is used, VBACKUP must be connected to VCC7 (main input supply). The VRTC LDO remains functional to power the real-time clock circuitry, and the BBCHEN bit in BBCH_REG should remain cleared to disable charging circuitry, preventing unintended current draw or regulation conflicts.