Texas Instruments TPS75005RGWR

Overview

TPS75005RGWR from Texas Instruments is a dual-LDO power management IC optimized for C2000™ real-time microcontrollers, delivering 500 mA at 1.8 V/1.9 V (VSET-selectable) and 500 mA at 3.3 V with ±5% output accuracy, dedicated SVS supervision per rail, and integrated sequencing logic. It enables compliant power-up/down for F2833x, F2823x, F281x, and F280x series in motor control and digital power applications.

For engineers reviewing the TPS75005RGWR datasheet, TPS75005RGWR pinout, TPS75005RGWR application, or TPS75005RGWR equivalent, this page provides verified specifications, QFN-20 package layout, sequencing behavior, supervisor thresholds, thermal performance data, and validated alternatives for C2000 MCU power design.

Technical Context

The TPS75005RGWR integrates two independent low-dropout regulators with dedicated voltage supervisors (SVS1/SVS2) and a third monitor (SVS3 on VMON), each with programmable delay via CT pins and hysteresis. Its sequencer responds to EN and SEQ inputs to enforce strict power-up order-LDO1-first or LDO2-first-and controlled power-down reversal.

It features separate soft-start control (SS1/SS2), active pull-down resistors (RPD1/RPD2), open-drain PG and VDET outputs with 100-kΩ pull-up recommendations, and thermal shutdown at +165°C with +20°C hysteresis. Input voltage range is 3.75 V to 6.5 V, supporting wide-input industrial supplies.

Key Specifications

Pinout & Package

TPS75005RGWR uses the RGW package: 5-mm × 5-mm QFN-20 with exposed thermal pad (Pin 21). Thermal pad must be soldered to PCB ground plane with ≥4×4 thermal via array for rated thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-LDO power management applications.

Compared with TPS75005RGWR, the TPS7H3301-SP adds radiation hardness at significant cost and availability trade-offs, while the TPS7A8300 offers superior noise performance but lacks integrated supervision and sequencing - making it unsuitable as a functional substitute for C2000 MCU power.

Availability

TPS75005RGWR is available at Aetrix Electronics and suitable for motor control systems, digital power controllers, and industrial PLC I/O modules requiring stable component supply, guaranteed long-term sourcing, and full traceability.

Supply support for TPS75005RGWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions for industrial, automotive, and communications markets.

The TPS75005RGWR belongs to TI's C2000-specific power management product line, engineered to eliminate discrete supervision and sequencing components in real-time MCU designs - reducing BOM count and improving system reliability.

FAQ

What is the function of the VSET pin on the TPS75005RGWR?

The VSET pin on the TPS75005RGWR selects the LDO1 output voltage: logic-high sets 1.9 V, logic-low sets 1.8 V. This matches the core voltage requirements of different C2000 MCU families (e.g., F2833x vs. F280x). The pin must be hard-wired to IN or GND - not driven dynamically - as transition timing is not characterized for runtime reconfiguration. TPS75005RGWR datasheet specifies ±5% accuracy for both settings across −40°C to +125°C.

How does the PG (Power-Good) signal behave on the TPS75005RGWR?

The PG pin on the TPS75005RGWR is an open-drain output that pulls high only when both LDO outputs exceed their respective supervisor thresholds (VOUT1 > VSVS1 and VOUT2 > VSVS2). It requires a 100-kΩ pull-up resistor to VOUT2. PG does not assert during soft-start ramp-up - it waits until both rails stabilize within specification. This behavior ensures the C2000 MCU receives a true "all-rails-good" signal before releasing reset, preventing premature boot. TPS75005RGWR guarantees PG assertion delay ≤33 µs after threshold crossing.

Can the TPS75005RGWR support custom power-up sequencing orders?

Yes - the TPS75005RGWR supports two fixed sequencing orders via the SEQ pin: logic-low powers LDO1 first then LDO2; logic-high reverses the order. This matches C2000 MCU dependencies - e.g., F2833x requires VDD before VDDIO, while some F280x variants require VDDIO first. Sequencing is hardware-controlled with no firmware involvement. TPS75005RGWR implements built-in soft-start per rail and inter-rail delay, eliminating need for external timers or CPLDs. The SEQ pin must be hard-wired, not toggled during operation.

What thermal design guidelines apply to the TPS75005RGWR QFN package?

The TPS75005RGWR RGW package requires the exposed thermal pad (Pin 21) to be soldered to a PCB ground plane with a minimum 4×4 array of thermal vias (0.3-mm diameter, 0.6-mm pitch) connecting to inner-layer copper pours. TI validates θJA = 35.1°C/W on a JEDEC high-K board; omitting vias or undersized copper increases junction temperature significantly. For 500-mA continuous load at 85°C ambient, thermal simulation shows >20°C margin to +165°C shutdown if layout follows SBVS144C Figure 26. TPS75005RGWR thermal metrics assume 1-oz internal and 2-oz bottom-layer copper spreaders.

Does the TPS75005RGWR include protection against input undervoltage or overtemperature?

Yes - the TPS75005RGWR includes undervoltage lockout (UVLO) with 60-mV hysteresis, disabling all outputs when VIN falls below ~3.4 V and re-enabling above ~3.75 V. It also features thermal shutdown at +165°C with +20°C hysteresis (releases at +145°C), protecting against sustained overload or inadequate heatsinking. Both protections are internal and require no external components. TPS75005RGWR datasheet confirms UVLO and TSD operate independently of EN state - they force shutdown even during active sequencing. No external circuitry is needed to implement these safeguards.