Texas Instruments TPS75005RGWT
- Part No.:
- TPS75005RGWT
- Manufacturer:
- Texas Instruments
- Category:
- Power Management - Specialized
- Package:
- 20-VQFN Exposed Pad
- Datasheet:
-
TPS75005RGWT.pdf
- Description:
- IC REG LDO 500MA DUAL 20VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,402
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Product details
Overview
TPS75005RGWT from Texas Instruments is a dual-LDO power management IC optimized for C2000™ real-time microcontrollers (F2833x, F2823x, F281x, F280x), delivering 500 mA at 1.8 V/1.9 V (VSET-selectable) and 500 mA at 3.3 V with ±5% output accuracy, dedicated SVS supervision per rail, and integrated sequencing logic. It supports transient-heavy MCU operation using two 10-µF ceramic output capacitors.
For engineers reviewing the TPS75005RGWT datasheet, TPS75005RGWT pinout, TPS75005RGWT application, or TPS75005RGWT equivalent, this page provides verified specifications, QFN-20 package layout, sequencing behavior under EN/SEQ control, thermal performance data (θJA = 35.1°C/W), and validated alternatives for C2000 power-rail replacement designs.
Technical Context
The TPS75005RGWT integrates two independent low-dropout regulators with dedicated voltage supervisors (SVS1/SVS2) and a third monitor (SVS3 via VMON) - each with programmable delay (CT1/CT2) and soft-start (SS1/SS2). Its sequencer enforces strict power-up/down order based on SEQ pin logic, ensuring compliance with C2000 MCU boot requirements.
It uses internal reference-based SVS thresholds (1.782 V / 1.818 V for LDO1; 3.267 V / 3.333 V for LDO2; 1.206 V for VMON) with 0.3% hysteresis and open-drain PG/VDET outputs requiring external pull-ups. All supervision signals feed into a centralized logic block that gates EN-driven sequencing and thermal shutdown (165°C trip, 145°C release).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.75 V to 6.5 V - supports wide-input industrial DC supplies and battery-backed systems without pre-regulation. |
| LDO1 Output | 1.818 V or 1.919 V (VSET-selectable), ±5% accuracy - meets C2000 core voltage tolerance with dedicated SVS1 supervision. |
| LDO2 Output | 3.333 V, ±5% accuracy - powers C2000 I/O rails with guaranteed SVS2 monitoring and PG assertion. |
| Output Current | 500 mA per LDO - sufficient for full-load F2833x/F2823x operation including flash programming and ADC sampling bursts. |
| Soft-Start Time | 260 µs (default, SS1/SS2 open) - prevents inrush current during cold start; adjustable via external capacitor. |
| Thermal Shutdown | 165°C trip, 145°C hysteresis - protects against sustained overload or poor PCB thermal design while allowing recovery. |
| Package | 5-mm × 5-mm QFN-20 with exposed thermal pad - enables compact layout and 35.1°C/W junction-to-ambient thermal resistance with standard JEDEC board. |
Pinout & Package
TPS75005RGWT is housed in a 5-mm × 5-mm QFN-20 package (RGW) with an exposed thermal pad soldered to PCB ground for enhanced heat dissipation. Pin numbering follows top-view orientation with Pin 1 at bottom-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN (Pins 18, 19) | Power input | Dual-input connection for low-impedance path to 10-µF input capacitor; minimizes voltage drop under load transients. |
| OUT1 (Pin 15), OUT2 (Pin 1) | LDO outputs | Deliver regulated 1.8/1.9 V and 3.3 V; require local 10-µF X5R/X7R ceramic capacitors for C2000 transient response. |
| OUT1_S (Pin 14), OUT2_S (Pin 2) | Voltage sense inputs | Connect directly to respective output capacitor terminals to enable remote-sense regulation and reject PCB trace IR drop. |
| EN (Pin 17) | Enable control | Active-high logic input; initiates full sequencing only after internal UVLO and thermal checks pass. |
| SEQ (Pin 8) | Sequencing mode select | Logic-L: LDO1→LDO2 up / LDO2→LDO1 down; Logic-H: reverse order - hard-wire to GND or IN for fixed behavior. |
| VSET (Pin 9) | LDO1 voltage select | Logic-L → 1.818 V; Logic-H → 1.919 V - sets core voltage for F280x/F281x (1.8 V) or F2833x/F2823x (1.9 V) compatibility. |
| PG (Pin 10) | Power-Good indicator | Open-drain output pulled to VOUT2; asserts high only when both VOUT1 > VSVS1 and VOUT2 > VSVS2 - synchronizes MCU reset release. |
| VDET (Pin 5) | VMON supervisor output | Open-drain output pulled to VIN; signals VMON > 1.206 V - used for input-voltage validation before enabling EN. |
| VMON (Pin 16) | Third-rail monitor input | Accepts resistor divider from monitored rail; triggers VDET when voltage exceeds 1.206 V threshold - supports auxiliary supply monitoring. |
| GND (Pins 6, 7) | Ground reference | Must connect to thermal pad and maximize copper area; forms low-inductance return path for both LDOs and supervisors. |
Key Features
| Feature | Design Value |
|---|---|
| Dual LDO + dual SVS per rail | Guarantees ±5% rail accuracy with independent supervision - eliminates need for external supervisors in C2000 designs. |
| Preset sequencing logic | Hardware-enforced power-up/down order via EN and SEQ pins - removes firmware dependency and ensures deterministic boot timing. |
| Adjustable soft-start and delay | SS1/SS2 and CT1/CT2 pins allow fine-tuning of ramp rate and supervisor timeout - accommodates custom timing margins beyond C2000 defaults. |
| Thermal-aware shutdown | 165°C trip with 20°C hysteresis - prevents thermal runaway during sustained 500-mA loads without derating. |
| Remote voltage sensing | OUT1_S/OUT2_S pins enable Kelvin connection to output caps - maintains regulation accuracy despite PCB trace resistance. |
Applications
| C2000 Real-Time MCU Power | DSP/FPGA Core + I/O Supply |
|---|---|
Use Scenario: Powering TI F28335 Delfino MCU in motor control inverters where precise core (1.9 V) and I/O (3.3 V) rails must meet ±5% tolerance during PWM switching transients. IC Role / Device Role / Timing Role: Dual-LDO PMIC providing regulated VDD and VDDIO with synchronized PG assertion and hardware-enforced startup sequence. Use Value: Eliminates discrete LDO + supervisor combinations, reduces BOM count by ≥4 components, and guarantees boot reliability under 10-A load steps. | Use Scenario: Supplying C6000 DSPs or Spartan-6 FPGAs requiring separate 1.8 V core and 3.3 V I/O rails with independent power-good signaling. IC Role / Device Role / Timing Role: Integrated dual-rail regulator with per-rail SVS and configurable sequencing - replaces two standalone LDOs plus two supervisors. Use Value: Enables single-chip solution for mixed-voltage digital systems, cuts PCB area by 40% vs discrete implementation, and simplifies layout with shared thermal pad. |
| Industrial PLC Controller | Automotive Body Control Module |
Use Scenario: Powering ARM-based PLC CPUs alongside analog front-ends where input voltage varies from 4.5 V to 6.0 V across 24-V system tolerances. IC Role / Device Role / Timing Role: Primary power manager with VMON input monitoring auxiliary 5-V rail and PG output coordinating system reset. Use Value: Supports wide VIN range without external buck converter; VMON supervision adds fault detection for redundant supply paths. | Use Scenario: Regulating MCU and CAN transceiver rails in body control units operating from 12-V battery with cold-crank dips to 4.0 V. IC Role / Device Role / Timing Role: Dual-output LDO with UVLO (3.75 V) and thermal shutdown - sustains operation through cranking events and prevents overheating in sealed enclosures. Use Value: Maintains functional safety during battery transients; PG signal ensures clean MCU reset upon recovery from undervoltage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-LDO power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7H3301-SP | Rad-hard quad-LDO with 3.3 V/2.5 V/1.8 V/1.2 V outputs; no integrated sequencing logic or SVS per rail. | Targeted at space-grade systems requiring radiation tolerance; lacks C2000-specific sequencing and PG coordination. | Select when radiation hardness is mandatory and external sequencing logic is acceptable. |
| TPS7A8300 | Single 3-A LDO with 1% accuracy and ultra-low noise; no second output, no SVS, no sequencing capability. | Designed for RF/analog supply domains; cannot replace dual-rail functionality or supervision of TPS75005RGWT. | Select only for high-current 3.3-V-only applications where noise performance outweighs integration needs. |
Compared with TPS7H3301-SP and TPS7A8300, the TPS75005RGWT uniquely combines dual 500-mA LDOs, per-rail ±5% SVS, hardware sequencing, and C2000-optimized timing - making it irreplaceable for cost-sensitive, space-constrained industrial MCU designs requiring guaranteed boot integrity.
Availability
TPS75005RGWT is available at Aetrix Electronics and suitable for industrial motor drives, PLC controllers, and automotive body electronics requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for TPS75005RGWT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in industrial and automotive electronics.
The TPS75005RGWT belongs to TI's C2000-specific power management product line, engineered to eliminate discrete power design complexity and ensure deterministic power sequencing for real-time microcontrollers in high-reliability applications.
FAQ
What is the function of the VSET pin on the TPS75005RGWT?
The VSET pin on the TPS75005RGWT selects the LDO1 output voltage: logic-low (≤0.8 V) configures 1.818 V for F280x/F281x MCUs, and logic-high (≥2.0 V) configures 1.919 V for F2833x/F2823x devices. This pin must be hard-wired to GND or IN - not dynamically toggled - as transition time is uncharacterized for runtime reconfiguration. The TPS75005RGWT datasheet specifies ±5% accuracy for both settings across –40°C to +125°C.
How does the TPS75005RGWT handle power sequencing for C2000 MCUs?
The TPS75005RGWT implements hardware-based sequencing controlled by the EN and SEQ pins: EN initiates the sequence, and SEQ determines order - logic-L powers LDO1 first then LDO2, while logic-H reverses it. Both power-up and power-down follow the same order. This eliminates software dependency and ensures repeatable timing critical for C2000 boot integrity. The TPS75005RGWT also incorporates soft-start (260 µs default) to limit inrush current during each stage.
Can the TPS75005RGWT monitor an external voltage rail?
Yes, the TPS75005RGWT monitors external rails via the VMON pin, which accepts a resistor divider to scale the target voltage down to its internal 1.206 V threshold. When the scaled voltage exceeds 1.206 V, the open-drain VDET pin pulls low; below threshold, VDET floats high (with external pull-up). This allows supervision of auxiliary supplies like 5-V bias rails or isolated DC-DC outputs - a feature confirmed in the TPS75005RGWT electrical characteristics table and functional block diagram.
What thermal performance can be expected from the TPS75005RGWT in a standard PCB layout?
In a JEDEC-standard high-K board with 4×4 thermal vias under the exposed pad, the TPS75005RGWT achieves θJA = 35.1°C/W. With 500-mA load on both LDOs at 6.5-V input, power dissipation reaches ~1.5 W, resulting in ~53°C junction rise above ambient - well within the 125°C max TJ rating. The TPS75005RGWT thermal metrics assume 1-oz internal and 2-oz bottom copper planes; reducing copper area increases θJA proportionally.
Is the TPS75005RGWT compatible with ceramic output capacitors?
Yes, the TPS75005RGWT is explicitly designed for stability with 10-µF X5R or X7R ceramic capacitors on both OUT1 and OUT2, as required by C2000 MCU transient specifications. The device's control loop compensates for low-ESR ceramics (≤1.0 Ω), eliminating need for series resistors or tantalum alternatives. The TPS75005RGWT datasheet confirms stability across –40°C to +125°C with these capacitors and specifies minimum 4.7-µF value for general use.
TPS75005RGWT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Applications:
- Microcontroller, MCU
- Current - Supply:
- 175µA
- Voltage - Supply:
- 3.75V ~ 6.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-VQFN (5x5)
TPS75005RGWT FAQ
1.How can I place an order for TPS75005RGWT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS75005RGWT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS75005RGWT reliable?
The price and inventory of TPS75005RGWT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS75005RGWT is usually 5 days.
3.What payment methods are accepted for TPS75005RGWT?
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4.How is shipping managed for TPS75005RGWT?
TPS75005RGWT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS75005RGWT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS75005RGWT?
For technical support, including TPS75005RGWT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS75005RGWT requirements.
6.How does Aetrix verify that TPS75005RGWT is sourced from the original manufacturer or authorized distributors?
All TPS75005RGWT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS75005RGWT meets industry standards.
7.What is the process for return or replacement of TPS75005RGWT?
All TPS75005RGWT units undergo pre-shipment inspection (PSI). If there is an issue with TPS75005RGWT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS75005RGWT part is unused and in its original packaging.
Return procedure for TPS75005RGWT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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