Texas Instruments UCC27524ADGN
- Part No.:
- UCC27524ADGN
- Manufacturer:
- Texas Instruments
- Category:
- Gate Drivers
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Datasheet:
-
UCC27524ADGN.pdf
- Description:
- IC GATE DRVR LOW-SIDE 8MSOP
- Quantity:
- Payment:

- Shipping:

Inventory:178
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Product details
Overview
UCC27524ADGN from Texas Instruments is a dual-channel, non-inverting, low-side gate driver IC designed to drive MOSFETs and IGBTs in high-frequency power stages. It delivers 5A peak source/sink current per channel, features 17ns typical propagation delay, 1ns typical inter-channel delay matching, and operates from 4.5V to 18V supply with –5V input voltage tolerance - enabling robust gate control in GaN-based DC-DC converters and synchronous rectifiers.
For engineers reviewing the UCC27524ADGN datasheet, UCC27524ADGN pinout, UCC27524ADGN application, or UCC27524ADGN equivalent, this page provides verified package mapping (HVSSOP-8), confirmed dual-channel timing behavior, validated negative-input-voltage capability (–5V), and real-world design implications of its rail-to-rail output stage, UVLO-controlled glitch-free startup, and independent enable logic.
Technical Context
The UCC27524ADGN implements two independent, non-inverting driver channels with TTL/CMOS-compatible inputs whose thresholds (1.0V low / 2.0V high) and 1V hysteresis are fully independent of VDD. Its hybrid pull-up output stage combines P- and N-channel MOSFETs to deliver 5A peak source current during the Miller plateau, while the dedicated N-channel pull-down ensures 5A sink capability and sub-10ns fall times.
Each channel includes a dedicated enable pin (ENA/ENB) with internal 200kΩ pull-up, allowing floating-enable operation for pin compatibility with UCC27324. The device holds outputs low during VDD UVLO (4.1V rising threshold) and when inputs float (via 120kΩ internal pulldown), ensuring fail-safe behavior at power-up, fault conditions, and system idle states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | ±5A per channel - enables direct drive of high-Qg GaN FETs and IGBTs without external buffers |
| Propagation Delay | 17ns typical - supports >5 MHz switching in resonant topologies with minimal timing skew |
| Delay Matching | 1ns typical between channels - critical for synchronous rectifier timing alignment and parallel-output current doubling |
| Input Voltage Range | –5V to 18V - allows direct connection to auxiliary rails or noisy gate-drive feedback paths without level-shifting |
| VDD Operating Range | 4.5V to 18V - accommodates 5V, 12V, and 15V bias supplies across industrial and telecom power designs |
| UVLO Threshold | 4.1V (rising), 3.8V (falling) - prevents erratic output behavior during brown-out and ensures clean power-up sequencing |
| Rise/Fall Time | 6ns/10ns (typ, 1.8nF load) - reduces switching losses and EMI in hard-switched and ZVS circuits |
Pinout & Package
HVSSOP-8 PowerPAD™ package (3.00mm × 3.00mm body, exposed thermal pad on underside) optimized for high-power density and thermal performance in compact DC-DC modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - ENA | Channel A enable input | Active-high logic; floats HIGH by internal 200kΩ pull-up - enables default operation without external bias |
| 2 - INA | Channel A non-inverting input | TTL/CMOS compatible; 120kΩ internal pulldown holds OUTA LOW if floating - prevents unintended turn-on |
| 3 - GND | Power and signal reference | Common return for VDD, inputs, enables, and outputs; connects to thermal pad for enhanced heat dissipation |
| 4 - INB | Channel B non-inverting input | Functionally identical to INA; supports independent or complementary drive of two switches |
| 5 - OUTB | Channel B output | Rail-to-rail (GND to VDD), ±5A capable - drives gate of low-side switch directly with minimal external components |
| 6 - VDD | Supply input | Single 4.5–18V rail powers both channels and internal logic; UVLO circuitry monitors this node exclusively |
| 7 - OUTA | Channel A output | Electrically identical to OUTB; matched delay enables precise paralleling for 10A total drive |
| 8 - ENB | Channel B enable input | Independent of ENA; allows asymmetric channel control for burst-mode or adaptive dead-time applications |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-channel enable | ENx pins allow selective shutdown of one driver without affecting the other - essential for light-load efficiency in synchronous rectifiers |
| –5V input voltage tolerance | Withstands negative transients on INA/INB/ENA/ENB - eliminates need for external clamping diodes in noisy motor-drive or solar inverter environments |
| Input threshold independence from VDD | Logic thresholds fixed at ~1.0V/2.0V regardless of supply voltage - guarantees reliable interface with 3.3V microcontrollers even at 18V VDD |
| Outputs held low during UVLO | Prevents partial turn-on of power switches at undervoltage - avoids shoot-through and thermal stress during startup or brownout |
| Matched 1ns inter-channel delay | Enables precise timing-critical configurations such as transformer-coupled gate drives and dual-phase synchronous rectification |
Applications
| Switch-Mode Power Supplies | DC-DC Converters |
|---|---|
Use Scenario: High-efficiency, high-density AC-DC adapters using synchronous rectification with dual low-side FETs. IC Role / Device Role / Timing Role: Dual low-side gate driver providing matched, fast-turning outputs to control SR FETs in continuous conduction mode (CCM). Use Value: 1ns delay matching minimizes cross-conduction risk; 5A drive sustains low RDS(on) FETs at >1MHz switching frequencies. |
Use Scenario: Isolated 48V-to-12V telecom DC-DC modules with GaN half-bridge and active clamp forward topology. IC Role / Device Role / Timing Role: Low-side driver for active clamp switch and synchronous rectifier, requiring negative input tolerance for gate-loop noise immunity. Use Value: –5V input rating eliminates external protection; 17ns propagation delay enables tight duty-cycle control in <100ns dead-time designs. |
| Solar Power Inverters | Motor Control Systems |
Use Scenario: String-level MPPT converters with bidirectional buck-boost stages using SiC MOSFETs. IC Role / Device Role / Timing Role: Dual-channel driver controlling low-side switches in interleaved phases, with independent enable for phase shedding. Use Value: Independent ENA/ENB allows dynamic phase management; 150°C max junction temperature supports uncooled outdoor deployment. |
Use Scenario: BLDC motor drives in industrial automation where gate-drive reliability under ESD and load dump is critical. IC Role / Device Role / Timing Role: Low-side driver for three-phase inverter leg low-side switches, interfacing with isolated PWM controllers. Use Value: 2kV HBM ESD rating and –5V input tolerance withstand motor back-EMF spikes and board-level transients without failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-side dual gate driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC27524ADR | SOIC-8 package (4.90mm × 3.91mm); higher RθJA (126.4°C/W vs 48.9°C/W); same electrical specs | Less suitable for thermally constrained, high-power-density layouts; requires larger PCB area and more copper | Select UCC27524ADR only when HVSSOP-8 assembly is unavailable or SOIC footprint reuse is mandatory. |
| LM5113SDX | Single-channel, 5A sink/source; no independent enable; 25ns propagation delay; 3.5–14V VDD range | Requires two units for dual-channel operation; lacks –5V input tolerance and inter-channel matching | Choose LM5113SDX only for cost-sensitive, space-tolerant single-channel designs where timing matching is not required. |
Compared with UCC27524ADR, the UCC27524ADGN offers superior thermal performance and smaller footprint; compared with LM5113SDX, it delivers true dual-channel synchronization, negative input resilience, and tighter timing control - making it the optimal choice for high-reliability, high-frequency power conversion.
Availability
UCC27524ADGN is available at Aetrix Electronics and suitable for switch-mode power supplies, DC-DC converters, and motor control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for industrial and automotive-grade production.
Supply support for UCC27524ADGN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs and high-reliability industrial solutions.
The UCC27524ADGN belongs to TI's UCC2752x family of high-speed gate drivers, engineered specifically for demanding power conversion applications including GaN/SiC-based SMPS, solar inverters, and motor drives where timing precision, noise immunity, and thermal robustness are critical.
FAQ
What is the maximum negative voltage the UCC27524ADGN inputs can tolerate?
The UCC27524ADGN inputs (INA, INB, ENA, ENB) are rated for –5V DC per Absolute Maximum Ratings. This specification allows direct connection to nodes experiencing negative transients - such as gate loops in high-dV/dt GaN circuits - without external clamping diodes. The UCC27524ADGN maintains functional integrity within this range, and operation below –5V risks permanent damage.
Does the UCC27524ADGN support paralleling of its two output channels?
Yes, the UCC27524ADGN supports safe paralleling of OUTA and OUTB to achieve up to 10A peak drive current. Its 1ns typical inter-channel delay matching and rail-to-rail output stage ensure balanced current sharing. To implement this, connect INA and INB together, tie ENA and ENB together, and route OUTA and OUTB to the same gate node - the UCC27524ADGN datasheet explicitly validates this configuration.
How does the UCC27524ADGN behave when its input pins are left floating?
When INA or INB is left floating, the UCC27524ADGN's internal 120kΩ pulldown resistor pulls the input low, forcing the corresponding output (OUTA or OUTB) to remain LOW. This fail-safe behavior prevents unintended power-switch turn-on during initialization, fault conditions, or open-circuit wiring - a key safety feature confirmed in the UCC27524ADGN Electrical Characteristics table and Functional Description section.
What is the purpose of the enable pins (ENA and ENB) on the UCC27524ADGN?
The ENA and ENB pins provide independent, active-high control over each output channel. When pulled LOW, they force the respective output to LOW regardless of the input state - enabling precise channel disable for burst-mode operation, light-load efficiency optimization, or fault isolation. The UCC27524ADGN includes internal 200kΩ pull-up resistors, so leaving ENA/ENB unconnected defaults to enabled operation, maintaining pin compatibility with legacy UCC27324 designs.
Is the UCC27524ADGN suitable for driving GaN power devices?
Yes, the UCC27524ADGN is explicitly recommended for GaN FETs in its Applications section and Feature Description. Its 5A peak source/sink current, 6ns rise time, 17ns propagation delay, and –5V input tolerance address GaN-specific needs: fast switching, Miller plateau drive strength, and resilience against gate-loop ringing. The UCC27524ADGN's rail-to-rail output and low VOL/VOH further ensure full enhancement and depletion of enhancement-mode GaN devices.
UCC27524ADGN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Low-Side
- Channel Type:
- Independent
- Number of Drivers:
- 2
- Gate Type:
- IGBT, N-Channel MOSFET
- Voltage - Supply:
- 4.5V ~ 18V
- Logic Voltage - VIL, VIH:
- 1V, 2.3V
- Current - Peak Output (Source, Sink):
- 5A, 5A
- Input Type:
- Non-Inverting
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- 7ns, 6ns
- Operating Temperature:
- -40°C ~ 140°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-HVSSOP
UCC27524ADGN FAQ
1.How can I place an order for UCC27524ADGN through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC27524ADGN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC27524ADGN reliable?
The price and inventory of UCC27524ADGN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC27524ADGN is usually 5 days.
3.What payment methods are accepted for UCC27524ADGN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC27524ADGN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC27524ADGN?
UCC27524ADGN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC27524ADGN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC27524ADGN?
For technical support, including UCC27524ADGN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC27524ADGN requirements.
6.How does Aetrix verify that UCC27524ADGN is sourced from the original manufacturer or authorized distributors?
All UCC27524ADGN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC27524ADGN meets industry standards.
7.What is the process for return or replacement of UCC27524ADGN?
All UCC27524ADGN units undergo pre-shipment inspection (PSI). If there is an issue with UCC27524ADGN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC27524ADGN part is unused and in its original packaging.
Return procedure for UCC27524ADGN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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