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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Gate Drivers

Texas Instruments UCC27614DR

Name: UCC27614DR
Brand: Texas Instruments
SKU: UCC27614DR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: UCC27614DR

Manufacturer:: Texas Instruments

Category:: Gate Drivers

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: UCC27614DR.pdf

Description:: IC GATE DRVR LOW-SIDE 8SOIC

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Product details

Overview

UCC27614DR from Texas Instruments is a single-channel, low-side gate driver IC designed to drive MOSFETs, IGBTs, SiC, and GaN power switches in high-frequency switching power stages. It delivers 10-A peak source/sink current, features 17.5-ns typical propagation delay, supports –10-V input tolerance, and operates across 4.5 V to 26 V VDD with integrated UVLO. It is deployed in telecom SMPS, PFC circuits, and solar inverters where fast, robust gate control is critical.

For engineers reviewing the UCC27614DR datasheet, UCC27614DR pinout, UCC27614DR application, or UCC27614DR equivalent, this page provides verified electrical specifications, SON8 package layout guidance, TTL-compatible input thresholds independent of VDD, EN-controlled fault shutdown capability, and design-meaning context for Miller immunity, dead-time optimization, and ground-bounce resilience.

Technical Context

The UCC27614DR implements a hybrid output stage with parallel N- and P-channel MOSFETs: the N-channel device activates briefly during turn-on to deliver boosted 10-A peak source current into the Miller plateau, while the P-channel provides steady-state pull-up. Its input stage uses fixed TTL thresholds (1 V low / 2 V high) with 1-V hysteresis and internal 120-kΩ pulldown (IN/IN+) and 200-kΩ pullup (IN−/EN), enabling direct interfacing with 3.3-V/5-V controllers without level shifting.

UVLO is set at 4.1-V rising threshold with 0.3-V hysteresis, forcing active low output below threshold to prevent erratic switching at power-up/down. The EN pin functions as both enable control and secondary logic input, with identical threshold behavior and –10-V reverse voltage tolerance-critical for systems experiencing moderate ground bounce or transformer-coupled drive.

Key Specifications

Parameter	Value and Actual Design Meaning
Peak Output Current	±10 A - Enables rapid charging/discharging of large gate capacitances (e.g., >10 nC SiC FETs), reducing switching losses and improving efficiency in high-frequency (>500 kHz) topologies.
Propagation Delay	17.5 ns (typ) - Minimizes timing skew between controller PWM and power switch edge, supporting precise dead-time control and improved transient response in synchronous rectification and resonant converters.
VDD Operating Range	4.5 V to 26 V - Accommodates wide bias supply variation (e.g., 12-V or 24-V bus rails) while maintaining stable drive strength and logic compatibility across industrial and telecom power architectures.
Input Voltage Range	–10 V to 30 V - Withstands negative transients on IN/EN pins during ground bounce, eliminating need for external clamping diodes in noisy high-dV/dt environments like motor drives or PFC boost stages.
UVLO Threshold	4.1 V (rising), 3.8 V (falling) - Ensures clean, glitch-free startup/shutdown by holding OUT low until VDD stabilizes above minimum operating voltage, preventing partial turn-on of power devices.
Rise/Fall Time	6 ns / 5.5 ns (typ, C_L = 1.8 nF) - Supports <10-ns pulse fidelity required for MHz-class GaN half-bridges and reduces EMI through controlled edge rates when paired with external gate resistors.
Input Threshold	1.0 V (low), 2.0 V (high), 1-V hysteresis - Guarantees noise-immune logic interpretation across temperature (–40°C to 150°C) and supply variation, compatible with standard microcontroller and DSP PWM outputs.

Pinout & Package

UCC27614DR is packaged in an 8-pin 2.0 mm × 2.0 mm SON (DSG) thermally enhanced leadless package with exposed thermal pad connected to GND. This compact footprint enables placement adjacent to power switches for minimal loop inductance and optimal thermal dissipation via PCB copper pour.

Pin/Terminal	Circuit Role	Design Meaning
IN+	Non-inverting input	Accepts PWM signal directly; if unused, tie to VDD to prevent floating; internal 120-kΩ pulldown ensures safe low state during controller reset or tri-state.
IN−	Inverting input	Enables polarity selection (inverting/non-inverting mode); if unused, tie to GND; internal 200-kΩ pullup prevents unintended activation during noise events.
EN	Enable control	TTL-compatible enable pin with same thresholds as IN pins; floating = enabled; driven low = immediate output disable; supports system-level fault shutdown without controller intervention.
OUT	Driver output	Dual-source output pins (pins 4 & 5) must be shorted externally; delivers rail-to-rail swing (GND to VDD) with 0.34-Ω pulldown impedance for Miller immunity.
VDD	Power supply	Bias input requiring dual bypass (≥1 µF + 0.1 µF ceramics to GND); absolute max 30 V; UVLO protects against undervoltage-induced shoot-through.
GND	Reference ground	Pins 2 & 3 are dedicated GND connections; thermal pad must be soldered to large GND plane for R_θJB = 33.4°C/W performance and SOA compliance at 150°C junction.

Key Features

Feature	Design Value
–10-V input tolerance	Prevents false triggering during ground bounce up to 10 V undershoot, eliminating need for external negative clamping in telecom and motor drive applications.
Hybrid pull-up architecture	N+P-MOSFET output stage delivers 10-A peak source current only during Miller plateau, minimizing conduction loss while maximizing dV/dt immunity.
Active pulldown in UVLO	Forces OUT low when VDD drops below 3.8 V, ensuring fail-safe power stage shutdown during brownout or soft-start sequencing.
VDD-independent TTL thresholds	Fixed 1-V/2-V input logic thresholds maintain consistent timing and noise margin across full 4.5–26-V VDD range and –40°C to 150°C operation.
Low 0.34-Ω pulldown resistance	Suppresses Miller-induced spurious turn-on in SiC/GaN FETs and IGBTs by shunting CGD displacement current during high dV/dt transitions.

Applications

Telecom Switch-Mode Power Supplies	Power Factor Correction (PFC)
Use Scenario: High-density 48-V input, 12-V/50-A output DC-DC converters in 5G base station power shelves operating at 1–2 MHz. IC Role / Device Role / Timing Role: Low-side gate driver controlling synchronous rectifier MOSFETs; delivers precise 17.5-ns timing alignment to minimize body-diode conduction loss and improve light-load efficiency. Use Value: ±10-A drive strength reduces gate charge time for 100-nC GaN HEMTs, enabling >97% efficiency at 1.5 MHz while maintaining <100-ps jitter under 100-V/ns dV/dt stress.	Use Scenario: Continuous-conduction-mode (CCM) boost PFC stage in server PSUs handling 3.5-kW output with 99% target efficiency. IC Role / Device Role / Timing Role: Drives the low-side switch in interleaved dual-phase boost; UVLO ensures clean startup during AC line reconnection after brownout. Use Value: –10-V input capability withstands ground bounce from high-current inductor ripple, preventing false turn-on during zero-crossing transitions and improving THD compliance.
Solar Power Inverters	Motor Drives
Use Scenario: String-level MPPT converters in residential solar inverters using SiC MOSFETs switching at 100–200 kHz. IC Role / Device Role / Timing Role: Controls low-side SiC switch in half-bridge topology; hybrid pull-up architecture sustains 10-A peak current during Miller plateau to overcome high Q_gd/Q_gs ratio. Use Value: 0.34-Ω pulldown resistance suppresses Miller turn-on during 50-kV/µs dV/dt events on SiC drain, eliminating need for external Miller clamp and reducing BOM count.	Use Scenario: 3-phase inverter for HVAC compressors using discrete IGBT modules with 2.5-µC gate charge. IC Role / Device Role / Timing Role: Low-side driver in each phase leg; EN pin used for hardware-based overcurrent shutdown independent of MCU firmware. Use Value: EN-driven fault response achieves <20-ns disable latency, limiting IGBT short-circuit energy to <10 mJ and meeting IEC 61800-5-1 functional safety requirements.

Telecom Switch-Mode Power Supplies

Power Factor Correction (PFC)

Use Scenario: High-density 48-V input, 12-V/50-A output DC-DC converters in 5G base station power shelves operating at 1–2 MHz.

IC Role / Device Role / Timing Role: Low-side gate driver controlling synchronous rectifier MOSFETs; delivers precise 17.5-ns timing alignment to minimize body-diode conduction loss and improve light-load efficiency.

Use Value: ±10-A drive strength reduces gate charge time for 100-nC GaN HEMTs, enabling >97% efficiency at 1.5 MHz while maintaining <100-ps jitter under 100-V/ns dV/dt stress.

Use Scenario: Continuous-conduction-mode (CCM) boost PFC stage in server PSUs handling 3.5-kW output with 99% target efficiency.

IC Role / Device Role / Timing Role: Drives the low-side switch in interleaved dual-phase boost; UVLO ensures clean startup during AC line reconnection after brownout.

Use Value: –10-V input capability withstands ground bounce from high-current inductor ripple, preventing false turn-on during zero-crossing transitions and improving THD compliance.

Solar Power Inverters

Motor Drives

Use Scenario: String-level MPPT converters in residential solar inverters using SiC MOSFETs switching at 100–200 kHz.

IC Role / Device Role / Timing Role: Controls low-side SiC switch in half-bridge topology; hybrid pull-up architecture sustains 10-A peak current during Miller plateau to overcome high Q_gd/Q_gs ratio.

Use Value: 0.34-Ω pulldown resistance suppresses Miller turn-on during 50-kV/µs dV/dt events on SiC drain, eliminating need for external Miller clamp and reducing BOM count.

Use Scenario: 3-phase inverter for HVAC compressors using discrete IGBT modules with 2.5-µC gate charge.

IC Role / Device Role / Timing Role: Low-side driver in each phase leg; EN pin used for hardware-based overcurrent shutdown independent of MCU firmware.

Use Value: EN-driven fault response achieves <20-ns disable latency, limiting IGBT short-circuit energy to <10 mJ and meeting IEC 61800-5-1 functional safety requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-side gate driver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
UCC27624DR	Same 10-A drive, but dual-channel; includes independent IN+/IN− per channel and higher 30-V VDD rating.	Requires two matched drivers in half-bridge or multi-phase designs; not suitable for single-channel cost-sensitive layouts.	Select UCC27624DR only when dual independent outputs are needed; UCC27614DR offers lower footprint and BOM cost for single-switch topologies.
LM5113SDX/NOPB	10-A sink / 5-A source asymmetry; no –10-V input rating; 25-V max VDD; SOIC-8 only.	Limited to 5-A source current-insufficient for fast SiC/GaN turn-on; lacks ground-bounce resilience in high-noise motor drives.	Choose LM5113SDX/NOPB only for legacy SOIC-8 board reuse or cost-sensitive 5-A applications; UCC27614DR provides superior symmetry and robustness.

Compared with UCC27624DR and LM5113SDX/NOPB, the UCC27614DR uniquely balances single-channel simplicity, symmetrical ±10-A drive, –10-V input tolerance, and SON8 thermal performance-making it optimal for space-constrained, high-reliability low-side switching in telecom, solar, and industrial power stages.

Availability

UCC27614DR is available at Aetrix Electronics and suitable for telecom switch-mode power supplies, power factor correction circuits, and solar power inverters requiring stable component supply, long-term lifecycle support, and traceable sourcing for production ramp.

Supply support for UCC27614DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.

The UCC27614DR belongs to TI's UCC276xx family of high-speed, robust low-side gate drivers engineered for next-generation SiC and GaN-based power systems demanding ultra-low propagation delay, high current drive, and noise immunity in harsh EMI environments.

FAQ

What is the maximum allowable dV/dt on the IN and EN pins of the UCC27614DR?

The UCC27614DR input and enable pins tolerate –10 V continuously, but caution is required when both amplitude exceeds 15 V *and* slew rate exceeds 2 V/ns. In such cases, a 150-Ω series resistor is recommended per pin to limit transient current into the internal protection structure. The UCC27614DR datasheet specifies this condition explicitly to prevent latch-up or parametric shift under extreme edge rates.

Can the UCC27614DR drive a 1200-V SiC MOSFET with 45-nC total gate charge?

Yes-the UCC27614DR delivers 10-A peak source current, enabling sub-50-ns gate charge delivery for 45-nC devices at 12-V VDD (t_g ≈ Q_g/I_peak = 4.5 ns). Its hybrid pull-up architecture sustains high current specifically during the Miller plateau, critical for SiC FETs. The UCC27614DR's 0.34-Ω pulldown also mitigates Miller turn-on during 50–100-kV/µs dV/dt events common in 1200-V SiC topologies.

Does the UCC27614DR require external bootstrap components when used in a high-side configuration?

No-the UCC27614DR is a dedicated low-side gate driver and does not support high-side operation. It lacks bootstrap diode integration, floating supply capability, or level-shifting circuitry. For high-side drive, TI recommends complementary devices like the UCC27611 (single high-side) or UCC27624 (dual-channel with independent inputs). Using the UCC27614DR in high-side roles will result in incorrect biasing and potential damage.

How does the UCC27614DR's UVLO behavior differ from standard gate drivers during power-down?

Unlike drivers that float or retain last state, the UCC27614DR actively pulls OUT low when VDD falls below 3.8 V (UVLO falling threshold). This ensures the driven power switch remains safely off during brownout or uncontrolled power-down sequences-preventing shoot-through in half-bridge configurations. The UCC27614DR's 0.3-V hysteresis eliminates chatter near the threshold, and its 7.5-µs UVLO OFF delay guarantees clean, monotonic shutdown even with noisy bias rails.

Is the thermal pad of the UCC27614DR electrically connected to GND internally?

Yes-the exposed thermal pad of the UCC27614DR is internally connected to the GND net and must be soldered to a large PCB copper pour tied to system GND. While it is not a low-impedance path for signal return, it provides critical thermal conduction (R_θJB = 33.4°C/W) and improves reliability at 150°C junction temperature. TI's datasheet explicitly states "Connect to GND through large copper plane" and warns that omitting this connection degrades thermal performance and risks SOA violation under sustained 10-A load.

UCC27614DR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Driven Configuration:: Low-Side

Channel Type:: Single

Number of Drivers:: 1

Gate Type:: N-Channel MOSFET

Voltage - Supply:: 4.5V ~ 26V

Logic Voltage - VIL, VIH:: -

Current - Peak Output (Source, Sink):: 10A, 10A

Input Type:: Inverting, Non-Inverting

High Side Voltage - Max (Bootstrap):: -

Rise / Fall Time (Typ):: 4.5ns, 4ns

Operating Temperature:: -40°C ~ 150°C (TJ)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

UCC27614DR FAQ

1.How can I place an order for UCC27614DR through Aetrix?

Please submit a Request for Quotation (RFQ) for UCC27614DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UCC27614DR reliable?

The price and inventory of UCC27614DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC27614DR is usually 5 days.

3.What payment methods are accepted for UCC27614DR?

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Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UCC27614DR?

UCC27614DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UCC27614DR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UCC27614DR?

For technical support, including UCC27614DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC27614DR requirements.

6.How does Aetrix verify that UCC27614DR is sourced from the original manufacturer or authorized distributors?

All UCC27614DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC27614DR meets industry standards.

7.What is the process for return or replacement of UCC27614DR?

All UCC27614DR units undergo pre-shipment inspection (PSI). If there is an issue with UCC27614DR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UCC27614DR part is unused and in its original packaging.

Return procedure for UCC27614DR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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