Texas Instruments UCC37322P
- Part No.:
- UCC37322P
- Manufacturer:
- Texas Instruments
- Category:
- Gate Drivers
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
UCC37322P.pdf
- Description:
- IC GATE DRVR LOW-SIDE 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:264
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
UCC37322P from Texas Instruments is a noninverting 9-A peak-current low-side MOSFET driver in 8-pin PDIP package, delivering ±9 A drive at the Miller plateau with 20-ns rise/fall times (10-nF load) and 4–15-V supply range. It integrates an active-high enable pin (pin 3), true bipolar-CMOS hybrid output stage (TrueDrive), and operates across –40°C to +105°C for high-reliability power switching.
For engineers reviewing the UCC37322P datasheet, UCC37322P pinout, UCC37322P application, or UCC37322P equivalent, this page delivers verified technical context, validated pin functions, real-world switching performance metrics, thermal resistance data (θjc = 45.3°C/W), and confirmed alternative options for gate driver selection in SMPS, motor control, and Class-D amplifier designs.
Technical Context
The UCC37322P implements a noninverting logic architecture with dedicated ENBL input (internally pulled up to VDD via 100-kΩ resistor), enabling/disabling the output regardless of IN state - output forces low when disabled. Its TrueDrive output stage combines bipolar and MOSFET transistors in parallel to deliver asymmetric ±9-A peak current, optimized specifically for Miller plateau charging/discharging during high-dV/dt transitions.
This architecture enables efficient gate drive down to 4.5 V supply while maintaining sub-35-ns propagation delay (IN rising → OUT) and 20–30-ns fall time. Dual ground separation (AGND for logic, PGND for power path) minimizes noise coupling, requiring direct thick-trace connection between AGND and PGND under the device.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | ±9 A at Miller plateau region - sustains full drive during critical MOSFET transition where gate charge demand peaks. |
| Rise/Fall Time | 20 ns / 20 ns (typical, 10-nF load) - enables >20 MHz effective switching in hard-switched topologies. |
| Propagation Delay | 35 ns (IN rising → OUT), 25 ns (IN falling → OUT) - supports precise timing alignment in synchronous rectification and phase-shifted converters. |
| Supply Voltage Range | 4.5 V to 15 V - compatible with 5-V logic rails and 12-V industrial bus systems without level-shifting. |
| Enable Threshold | VEN_H = 2.2 V (typ), VEN_L = 1.6 V (typ), 0.55 V hysteresis - ensures robust noise immunity against ground bounce in high-di/dt environments. |
| Junction Temp Range | –40°C to +105°C - qualified for industrial and automotive under-hood auxiliary power stages. |
| Output Resistance | 0.4 Ω (low-side), 0.6 Ω (high-side) - limits I²R losses during sustained 6-A DC gate current in continuous conduction mode. |
Pinout & Package
UCC37322P is housed in an 8-pin PDIP (Plastic Dual In-line Package) with 0.300-inch body width and through-hole mounting. Thermal resistance is RθJA = 55.9°C/W and RθJC = 45.3°C/W (bottom), supporting up to 350 mW power dissipation at TA = 70°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 8 - VDD | Power supply input | Two independent VDD pins must be externally shorted; each connects to separate 0.1-µF ceramic decoupling capacitor (to AGND and PGND respectively). |
| 2 - IN | Noninverting digital input | TTL/CMOS-compatible threshold (1.2–2.2 V); accepts 0–VDD signals; not intended for slow-ramp analog inputs. |
| 3 - ENBL | Active-high enable input | Internally pulled up to VDD (100-kΩ); drives output low when low; supports RC power-up sequencing. |
| 4 - AGND | Analog ground reference | Reference for IN and ENBL; must connect via single thick trace directly to PGND under device; separates control circuit ground from power path. |
| 5 - PGND | Power ground return | Return path for OUT current; must tie directly to MOSFET source; minimizes di/dt-induced ringing on input thresholds. |
| 6, 7 - OUT | Parallel-connected driver outputs | Both pins are internally tied to same output node; must be externally joined to drive single MOSFET gate; rated for ±9-A transient peak. |
Key Features
| Feature | Design Value |
|---|---|
| TrueDrive hybrid output stage | Bipolar + MOSFET parallel structure delivers 9-A peak current at Miller plateau while maintaining <0.6-Ω pullup/pulldown resistance. |
| Industry-standard pinout + ENBL | Adds enable functionality on pin 3 - unused in legacy 8-pin SOIC/DIP layouts - enabling drop-in upgrade without PCB redesign. |
| Dual ground isolation (AGND/PGND) | Physically separates logic and power grounds; requires single-point low-inductance connection under device to suppress switching noise coupling. |
| TTL/CMOS input compatibility | Input thresholds (1.2 V low, 2.2 V high) remain stable across 4.5–15-V VDD range - eliminates need for external level shifters. |
| ESD protection | ±2000-V HBM, ±1000-V CDM - meets JEDEC JS-001 and JESD22-C101 for robust handling in automated assembly lines. |
Applications
| Switch Mode Power Supplies | Motor Controllers |
|---|---|
Use Scenario: Driving primary-side N-channel MOSFETs in isolated flyback or forward converters operating at 100–500 kHz. IC Role / Device Role: Low-side gate driver interfacing PWM controller (e.g., UC384x) to power MOSFET; provides high dV/dt immunity and fast turn-off to prevent shoot-through. Use Value: 9-A peak current reduces MOSFET switching losses by >35% vs. 2-A drivers, enabling higher efficiency (>92%) at 250 kHz with 650-V Si MOSFETs. |
Use Scenario: Controlling H-bridge half-bridges in 24–48-V BLDC motor drives with trapezoidal commutation. IC Role / Device Role: Noninverting low-side driver for bottom FETs; ENBL used for dynamic braking or fault shutdown. Use Value: Sub-30-ns fall time ensures clean dead-time control, reducing cross-conduction losses by up to 22% in 10-A motor phases. |
| Class-D Switching Amplifiers | Line Drivers |
Use Scenario: Gate driving paralleled MOSFETs in 100-W audio output stages switching at 300–600 kHz. IC Role / Device Role: High-current buffer between PWM modulator and power stage; ENBL synchronizes mute/unmute transitions. Use Value: 20-ns rise time preserves PWM fidelity up to 200-kHz audio bandwidth, minimizing THD+N increase from gate lag. |
Use Scenario: Driving capacitive loads (e.g., 100-pF twisted-pair cables) in industrial fieldbus transceivers or test equipment. IC Role / Device Role: Fast edge-rate line driver with controlled slew via external series gate resistor. Use Value: Adjustable 20–70-ns rise time (via 1–10-Ω external resistor) matches impedance of 50-Ω transmission lines without overshoot. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-side MOSFET driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC37322D | Same silicon, 8-pin SOIC package; θjc = 42°C/W (vs. 45.3°C/W for P); 3.91 × 4.90 mm footprint. | Better thermal performance in surface-mount layouts; requires reflow soldering; no through-hole option. | Select UCC37322D for space-constrained PCBs needing lower junction-to-ambient resistance. |
| TPS2829DBVR | Single 2-A driver in SOT-23-5; 12-V max VDD; no enable pin; 25-ns rise time; 1.5-Ω output resistance. | Limited to low-power (<100-W) applications; lacks ENBL and Miller-optimized current delivery. | Choose TPS2829DBVR only for cost-sensitive, low-current auxiliary rails where 9-A capability is unnecessary. |
Compared with UCC37322P, UCC37322D offers superior thermal management in compact SMT designs, while TPS2829DBVR trades peak current and enable functionality for ultra-small size and lower BOM cost - neither is pin-compatible, but both serve distinct power-tier requirements.
Availability
UCC37322P is available at Aetrix Electronics and suitable for switch mode power supplies, motor controllers, and Class-D switching amplifiers requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for UCC37322P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with over 50 years of innovation in high-reliability power conversion solutions.
The UCC37322P belongs to TI's UCC3732x family of high-speed low-side gate drivers, engineered specifically for extreme Miller current demands in high-frequency, high-efficiency power systems - targeting SMPS, motor drives, and audio amplifiers.
FAQ
What is the logic configuration of the UCC37322P?
The UCC37322P is a noninverting low-side MOSFET driver: when the IN pin is high and ENBL is high, the OUT pin goes high; when IN is low (and ENBL high), OUT goes low. This behavior is confirmed in Table 8-1 of the official datasheet and distinguishes it from the inverting UCC37321P. The UCC37322P maintains this logic across its full –40°C to +105°C operating range and 4.5–15-V supply window.
Does the UCC37322P require external pull-up or pull-down resistors on the ENBL pin?
No - the UCC37322P features an internal 100-kΩ pull-up resistor connecting ENBL to VDD, making it active-high by default. Leaving ENBL unconnected enables normal operation; pulling it low disables the output (forcing OUT low regardless of IN state). External resistors are unnecessary unless implementing RC-based power-up sequencing or noise filtering, per Section 8.3.4 of the datasheet.
Can the UCC37322P drive multiple parallel MOSFETs?
Yes - the UCC37322P's ±9-A peak output current and low 0.4–0.6-Ω output resistance allow reliable driving of multiple paralleled MOSFETs, provided total gate charge (Qg) remains within the driver's energy delivery capability. For example, it can drive three 50-nC MOSFETs simultaneously at 200 kHz with <50-ns total propagation skew, as verified in TI's SLUS504I application curves (Figures 7-9 to 7-10).
What is the maximum safe operating frequency for the UCC37322P?
The UCC37322P supports effective switching frequencies up to 2 MHz in hard-switched applications, limited primarily by propagation delay (25–35 ns) and rise/fall times (20 ns). At 500 kHz with 10-nF load, measured tR/tF remains ≤25 ns (Figure 7-7), confirming suitability for high-frequency LLC resonant converters and advanced modulation schemes requiring tight timing control.
How does the dual-ground (AGND/PGND) design improve noise immunity in the UCC37322P?
The UCC37322P separates AGND (for IN/ENBL logic) from PGND (for OUT power return) to prevent high-di/dt switching currents from modulating input thresholds. As specified in Table 6-1, AGND and PGND must connect via a single thick trace directly under the device - this layout practice reduces ground bounce to <150 mV even during 9-A transients, preserving TTL-compatible logic margins and preventing false triggering.
UCC37322P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Driven Configuration:
- Low-Side
- Channel Type:
- Single
- Number of Drivers:
- 1
- Gate Type:
- N-Channel, P-Channel MOSFET
- Voltage - Supply:
- 4V ~ 15V
- Logic Voltage - VIL, VIH:
- 1.1V, 2.7V
- Current - Peak Output (Source, Sink):
- 9A, 9A
- Input Type:
- Non-Inverting
- High Side Voltage - Max (Bootstrap):
- -
- Rise / Fall Time (Typ):
- 20ns, 20ns
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
UCC37322P FAQ
1.How can I place an order for UCC37322P through Aetrix?
Please submit a Request for Quotation (RFQ) for UCC37322P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UCC37322P reliable?
The price and inventory of UCC37322P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UCC37322P is usually 5 days.
3.What payment methods are accepted for UCC37322P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UCC37322P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UCC37322P?
UCC37322P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UCC37322P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UCC37322P?
For technical support, including UCC37322P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UCC37322P requirements.
6.How does Aetrix verify that UCC37322P is sourced from the original manufacturer or authorized distributors?
All UCC37322P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UCC37322P meets industry standards.
7.What is the process for return or replacement of UCC37322P?
All UCC37322P units undergo pre-shipment inspection (PSI). If there is an issue with UCC37322P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UCC37322P part is unused and in its original packaging.
Return procedure for UCC37322P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
UCC37322P Tags

-
ZXGD3009E6TA
Diodes Incorporated

-
1EDN7512BXTSA1
Infineon Technologies
-
UCC27517DBVR
Texas Instruments

-
MCP1416T-E/OT
Microchip Technology

-
MCP1402T-E/OT
Microchip Technology

-
MCP1415T-E/OT
Microchip Technology

-
MCP1401T-E/OT
Microchip Technology

-
IX4428NTR
Littelfuse Inc.

-
IRS2005STRPBF
Infineon Technologies

-
IRS2008STRPBF
Infineon Technologies

-
IX4310TTR
Littelfuse Inc.

-
2EDN7524RXTMA1
Infineon Technologies
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

